Patents by Inventor Suman K. Banerjee

Suman K. Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9048110
    Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 2, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
  • Publication number: 20130207229
    Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 15, 2013
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
  • Patent number: 7741718
    Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 22, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Suman K. Banerjee, Alain C. Duvalley, Olin L. Hartin, Craig Jasper, Walter Parmon
  • Patent number: 7683483
    Abstract: Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (Lm). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Sandra J. Wipf
  • Patent number: 7683486
    Abstract: Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Suman K. Banerjee, Alain C. Duvallet, Craig Jasper, Olin L. Hartin, Walter Parmon
  • Publication number: 20100065968
    Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Suman K. Banerjee, Alain C. Duvallet, Olin L. Hartin, Craig Jasper, Walter Parmon
  • Publication number: 20090302440
    Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
    Type: Application
    Filed: July 30, 2009
    Publication date: December 10, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
  • Patent number: 7608913
    Abstract: An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: October 27, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
  • Publication number: 20080185686
    Abstract: Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (Lm). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.
    Type: Application
    Filed: February 5, 2007
    Publication date: August 7, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Sandra J. Wipf
  • Patent number: 7341915
    Abstract: Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material is deposited over a portion of the top gate structure. Then, the hardmask and top gate structure are encapsulated with an insulating material to form a spacer. A channel structure is formed from the channel layer, and the channel structure is disposed under the spacer. A bottom gate structure is formed from the bottom gate layer, and the bottom gate structure is disposed under the channel structure. Then, a source/drain contact is formed around the bottom gate structure.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: March 11, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip Li, Suman K. Banerjee, Thuy B. Dao, Olin L. Hartin, Jay P. John
  • Patent number: 7138686
    Abstract: A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is connected to an N well ring (124) of the first noise sensitive circuit (120) to collect noise from the substrate (110) and isolate the circuit from the P well region (112). A ground protected pad (304) is connected to an isolated P well (126) of a first noise sensitive circuit (120). The ground pad (304) collects noise from the isolated P well (126) and sends it to ground. A dedicated ground isolation pad (306) is connected to a P well ring (224) of a second noise sensitive circuit (220). The dedicated ground isolation pad (306) collects noise from the P well ring (224) and sends it to ground.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: November 21, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Suman K. Banerjee, Enrique Ferrer, Olin L. Hartin, Radu M. Secareanu