Patents by Inventor Sumer Can

Sumer Can has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528634
    Abstract: A voltage comparator contains low voltage devices (e.g., bipolar or MOS transistors) and high voltage devices (e.g., DMOS transistors). The low voltage devices, which cannot sustain a voltage greater than a relatively small range of variation that is substantially less than the range of potential variation of the input voltage, are connected in a differential amplifier configuration to perform precision differential measurements on the input voltage. The high voltage devices are interconnected with the low voltage devices in a manner that enables operating levels of the low voltage devices to move up/down, or ‘slide’, with variations in the input voltage, so that the low voltage devices are effectively immune to high levels of the input voltage.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 5, 2009
    Assignee: Intersil Americas Inc.
    Inventor: Sumer Can
  • Publication number: 20080001636
    Abstract: A voltage comparator contains low voltage devices (e.g., bipolar or MOS transistors) and high voltage devices (e.g., DMOS transistors). The low voltage devices, which cannot sustain a voltage greater than a relatively small range of variation that is substantially less than the range of potential variation of the input voltage, are connected in a differential amplifier configuration to perform precision differential measurements on the input voltage. The high voltage devices are interconnected with the low voltage devices in a manner that enables operating levels of the low voltage devices to move up/down, or ‘slide’, with variations in the input voltage, so that the low voltage devices are effectively immune to high levels of the input voltage.
    Type: Application
    Filed: June 28, 2006
    Publication date: January 3, 2008
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Sumer Can
  • Patent number: 7075804
    Abstract: A tracking soft start circuit architecture contains a plurality of soft start circuits for generating a plurality of soft start voltages during startup for application to associated power supply terminals of a power supply system. The soft start circuits are interconnected in such a manner that prevents any soft start circuit from generating a soft start voltage waveform until all of the controlled power output devices have been brought to the same prescribed state of operation, that is, all power FET gates are precharged and their source voltages match each other.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: July 11, 2006
    Assignee: Intersil Americas Inc.
    Inventors: William Brandes Shearon, Raymond Louis Giordano, Sumer Can
  • Patent number: 7005924
    Abstract: The current limiting circuit of the present invention includes a transconductance amplifier having two outputs and forming a conventional feedback loop. A first output connects to an output transistor and a second output is a replica output used to form a rapid response feedforward path to control the gate of the output transistor, for example, an external MOSFET.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: February 28, 2006
    Assignee: Intersil Americas Inc.
    Inventors: Sumer Can, William B. Shearon, Raymond Giordano
  • Patent number: 6965266
    Abstract: A high voltage differential amplifier including an input differential pair of low voltage transistors, a sense differential pair of low voltage transistors, first and second high voltage transistors, a low voltage bias transistor, a cascaded pair of low voltage transistors, and an output pair of high voltage transistors. The sense differential pair has a pair of control terminals that detect a common mode voltage of the differential input signal, and establishes a sense node which follows the common mode voltage. The first high voltage device is coupled to the sense node to establish bias node voltage levels which track the common mode voltage, including an output bias node biasing the output pair and a cascade bias node biasing the cascaded pair. In this manner, the terminals of the low voltage devices slide up or down with the common mode voltage and are protected from high voltage levels.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: November 15, 2005
    Assignee: Intersil America's Inc.
    Inventor: Sumer Can
  • Publication number: 20050184809
    Abstract: The current limiting circuit of the present invention includes a transconductance amplifier having two outputs and forming a conventional feedback loop. A first output connects to an output transistor and a second output is a replica output used to form a rapid response feedforward path to control the gate of the output transistor, for example, an external MOSFET.
    Type: Application
    Filed: July 8, 2004
    Publication date: August 25, 2005
    Applicant: Intersil Americas Inc.
    Inventors: Sumer Can, William Shearon, Raymond Giordano
  • Publication number: 20050105307
    Abstract: A tracking soft start circuit architecture contains a plurality of soft start circuits for generating a plurality of soft start voltages during startup for application to associated power supply terminals of a power supply system. The soft start circuits are interconnected in such a manner that prevents any soft start circuit from generating a soft start voltage waveform until all of the controlled power output devices have been brought to the same prescribed state of operation, that is, all power FET gates are precharged and their source voltages match each other.
    Type: Application
    Filed: January 14, 2004
    Publication date: May 19, 2005
    Applicant: Intersil Americas Inc. State of Incorporation: Delaware
    Inventors: William Shearon, Raymond Giordano, Sumer Can
  • Patent number: 6362652
    Abstract: An input circuit allows input buffers fabricated using submicron CMOS technologies to receive input signals having a voltage swing of 5V. The input circuit uses a cascode transistor to bias the drain of the input transistor so that the VGD of the input transistor does not reach or exceed the gate-oxide breakdown voltage. Outputs of the input buffers have a maximum voltage that is limited by their respective supply voltages.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: March 26, 2002
    Assignee: Fujitsu Microelectronics, Inc.
    Inventors: Mustafa Ertugrul Oner, Sumer Can
  • Patent number: 6149299
    Abstract: An apparatus and method for directly measuring the operating temperature of a semiconductor device. A temperature sensor is placed directly on the substrate containing the device whose temperature is of interest. The circuitry used to process the sensor signals is on a separate substrate. Because the sensor is on the same substrate as the device of interest, noise is produced in the sensor signals as a result of electrons injected into the substrate by the device. The present invention includes methods for cancelling the noise and error in the temperature measurements to provide a very accurate determination of the device's operating temperature.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: November 21, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Mehmet Aslan, Sumer Can
  • Patent number: 6016051
    Abstract: A bandgap reference circuit capable of operating at low voltage provides an adjustable bandgap reference voltage. The bandgap reference circuit includes a proportional to absolute temperature (PTAT) current source, a bias current source, two resistors and a transistor. The base of the transistor couples to the IPTAT current source and the emitter of the transistor couples to the bias current source. The bandgap reference circuit also includes two resistors. The first resistor couples between the emitter and the base of the transistor, and the second resistor couples to the base of the transistor. The first resistor receives a portion of the bias current and provides a current proportional to a base-emitter voltage of the transistor. The second resistor receives the PTAT current and the current proportional to the base-emitter voltage of the transistor and provides a reference voltage which remains substantially constant over temperature and which is proportional to a silicon bandgap voltage.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: January 18, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Sumer Can
  • Patent number: 5877974
    Abstract: A four-quadrant analog signal multiplier circuit with a folded cascode differential input stage allows such circuit to be operated at lower power supply voltage potentials, while allowing the same transistor types to be used for both sets of input signals thereby providing for more closely matched input device characteristics and signal gains.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: March 2, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Sumer Can
  • Patent number: 4896333
    Abstract: A transceiver device has a transmitter circuit for transmitting data from a local data terminal to a computer network. The transmitter circuit has a voltage-to-current converter including a voltage divider with a plurality of voltage threshold taps, each voltage tap having a fixed voltage level; and a plurality of differential current switches each having first and second differential inputs, and a current differential output. Each of the first differential inputs is connected in common for receiving a voltage signal, and the second differential inputs are connected to an associated one of the voltage threshold taps. The current switch outputs are directly connected to a common node, to provide a current signal stepwise the same as the voltage signal. Preferably the common node is connected to a current amplifier including a simple filter. The output current waveform is preferably a trapezoidal waveform having matched rise and fall times.
    Type: Grant
    Filed: August 4, 1987
    Date of Patent: January 23, 1990
    Assignee: Signetics Corporation
    Inventor: Sumer Can