Patents by Inventor Sumie Aoki

Sumie Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9298210
    Abstract: The present technology provides an excellent advantageous effect in terms of reducing power consumption of a bus system adapted to treat a transaction as a unit. Disclosed herein is a clock gating circuit including: a clock enable signal generation portion adapted to count the number of outstanding transactions in each of a plurality of regions into which a bus system is divided so as to generate a clock enable signal for each of the plurality of regions; and a masked clock generation portion adapted to mask a clock by using the clock enable signal for each of the plurality of regions so as to generate a masked clock.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: March 29, 2016
    Assignee: SONY CORPORATION
    Inventor: Sumie Aoki
  • Patent number: 8601191
    Abstract: Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 3, 2013
    Assignee: Sony Corporation
    Inventors: Sumie Aoki, Yoshito Katano
  • Publication number: 20120079150
    Abstract: Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.
    Type: Application
    Filed: July 27, 2011
    Publication date: March 29, 2012
    Applicant: Sony Corporation
    Inventors: Sumie Aoki, Yoshito Katano