Patents by Inventor Sumihiro Ichikawa

Sumihiro Ichikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11510647
    Abstract: A backing member includes: a resin body including a lower surface and an upper surface opposite to each other; a plurality of leads each of which extends in a first direction from the lower surface toward the upper surface, and that are embedded at pitches in the resin body; and a plurality of insulating spacers each of which is provided between adjacent ones of the leads and extends in a second direction intersecting with the first direction, and that contact the leads.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 29, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Sumihiro Ichikawa
  • Publication number: 20190231308
    Abstract: A backing member includes: a resin body including a lower surface and an upper surface opposite to each other; a plurality of leads each of which extends in a first direction from the lower surface toward the upper surface, and that are embedded at pitches in the resin body; and a plurality of insulating spacers each of which is provided between adjacent ones of the leads and extends in a second direction intersecting with the first direction, and that contact the leads.
    Type: Application
    Filed: January 25, 2019
    Publication date: August 1, 2019
    Inventor: Sumihiro Ichikawa
  • Patent number: 9960120
    Abstract: A wiring substrate includes a buried substrate disposed within a through-hole penetrating through a resin substrate of a core layer and including a plate-like body and a plurality of linear conductors penetrating the plate-like body, a first insulating layer covering a first surface of the resin substrate, a first wiring layer including a first pad pattern formed on a first surface of the buried substrate and a first wiring pattern formed on a first surface of the first insulating layer, and a third wiring pattern formed on the first surface of the resin substrate and covered by the first insulating layer. In the plurality of linear conductors, a gap between the adjacent linear conductors is smaller than a diameter of each of the linear conductors. The third wiring pattern is formed so as to have a thickness thicker than a thickness of the first wiring pattern.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 1, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Ryo Fukasawa, Sumihiro Ichikawa, Michio Horiuchi
  • Patent number: 9922960
    Abstract: A packaging structure includes a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first metal terminal; and a second substrate including a third metal terminal and a fourth metal terminal whose height is lower than the height of the third metal terminal, the second substrate being provided on the first substrate, the first metal terminal and the third metal terminal being directly bonded with each other, and the second metal terminal and the fourth metal terminal being bonded via a connection portion.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 20, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Sumihiro Ichikawa
  • Patent number: 9824993
    Abstract: A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 21, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Sumihiro Ichikawa
  • Publication number: 20170033071
    Abstract: A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers.
    Type: Application
    Filed: July 6, 2016
    Publication date: February 2, 2017
    Inventor: Sumihiro ICHIKAWA
  • Publication number: 20170025387
    Abstract: A packaging structure includes a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first metal terminal; and a second substrate including a third metal terminal and a fourth metal terminal whose height is lower than the height of the third metal terminal, the second substrate being provided on the first substrate, the first metal terminal and the third metal terminal being directly bonded with each other, and the second metal terminal and the fourth metal terminal being bonded via a connection portion.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 26, 2017
    Inventor: Sumihiro ICHIKAWA
  • Publication number: 20160293535
    Abstract: A wiring substrate includes a buried substrate disposed within a through-hole penetrating through a resin substrate of a core layer and including a plate-like body and a plurality of linear conductors penetrating the plate-like body, a first insulating layer covering a first surface of the resin substrate, a first wiring layer including a first pad pattern formed on a first surface of the buried substrate and a first wiring pattern formed on a first surface of the first insulating layer, and a third wiring pattern formed on the first surface of the resin substrate and covered by the first insulating layer. In the plurality of linear conductors, a gap between the adjacent linear conductors is smaller than a diameter of each of the linear conductors. The third wiring pattern is formed so as to have a thickness thicker than a thickness of the first wiring pattern.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 6, 2016
    Inventors: Ryo Fukasawa, Sumihiro Ichikawa, Michio Horiuchi
  • Patent number: 9048225
    Abstract: A semiconductor device includes a semiconductor substrate. A through hole extends through the semiconductor substrate. A first insulating layer covers an upper surface of the semiconductor substrate and includes an opening in communication with the through hole. An insulating film covers wall surfaces of the through hole and the opening. A through electrode is formed in the through hole and the opening. A first connection terminal includes an electroless plating metal layer formed on an end surface of the through electrode and an end surface of the insulating film. The first connection terminal has a larger diameter than the through electrode. A wiring pattern is laminated on a lower surface of the semiconductor substrate. An electrode pad is connected to the wiring pattern. The through electrode is connected to the wiring pattern.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 2, 2015
    Assignee: Shinko Electric Industries Co., LTD.
    Inventors: Sumihiro Ichikawa, Takaharu Yamano
  • Publication number: 20140239508
    Abstract: A semiconductor device includes a semiconductor substrate. A through hole extends through the semiconductor substrate. A first insulating layer covers an upper surface of the semiconductor substrate and includes an opening in communication with the through hole. An insulating film covers wall surfaces of the through hole and the opening. A through electrode is formed in the through hole and the opening. A first connection terminal includes an electroless plating metal layer formed on an end surface of the through electrode and an end surface of the insulating film. The first connection terminal has a larger diameter than the through electrode. A wiring pattern is laminated on a lower surface of the semiconductor substrate. An electrode pad is connected to the wiring pattern. The through electrode is connected to the wiring pattern.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: Shinko Electric Industries Co., LTD.
    Inventors: Sumihiro Ichikawa, Takaharu Yamano
  • Patent number: 7977569
    Abstract: A solar cell module is provided with a plurality of dye sensitized solar cells arranged on a plane and connected in series with an intercell region interposed therebetween. A first transparent substrate, a first transparent conductive film, a dye carrying oxide semiconductor layer, an electrolyte layer, a catalyst layer, a second transparent conductive film and a second transparent substrate are laminated. An insulating barrier seals cells on both sides thereof in fluid tightness and insulates them in the intercell region. An electrode connecting portion provided in a vertical central part of the insulating barrier connects an extended portion of the first transparent conductive film of one of the cells to that of a second transparent conductive film of the other cell, and the electrode connecting portion penetrates through at least one of the first transparent substrate and the second transparent substrate in the vertical direction and is thus exposed.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: July 12, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Sumihiro Ichikawa, Koji Takei, Noriyasu Shimizu, Yasunari Suzuki, Ryo Fukasawa, Daisuke Matono, Yuichiro Shimizu
  • Patent number: 7648906
    Abstract: A method and apparatus for processing a thin film able to easily form grooves in a conductive thin film on an insulating substrate, comprising bringing a first electrode into contact with the conductive thin film, maintaining a conductive state between a tip of a second electrode with a voltage applied with respect to the first electrode and the surface of the conductive thin film, and using the tip of the second electrode to scan the conductive thin film so as to thereby form grooves passing through the thickness of the conductive thin film and exposing the surface of the insulating substrate at their bottoms in the conductive thin film.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: January 19, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Koji Takei, Sumihiro Ichikawa, Yasunari Suzuki, Ryo Fukasawa, Daisuke Matono
  • Publication number: 20080236662
    Abstract: In a solar cell module in which a plurality of dye sensitized solar cells is arranged on a plane basis and is connected in series with an intercell region interposed therebetween, a first transparent substrate, a first transparent conductive film, a dye carrying oxide semiconductor layer, an electrolyte layer, a catalyst layer, a second transparent conductive film and a second transparent substrate are laminated, an insulating barrier seals cells on both sides thereof in fluid tightness and insulates them in the intercell region, an electrode connecting portion provided in a central part in a vertical direction of the insulating barrier connects an extended portion of the first transparent conductive film of one of the cells on the both sides to that of a second transparent conductive film of the other cell, and the electrode connecting portion penetrates through at least one of the first transparent substrate and the second transparent substrate in the vertical direction and is thus exposed.
    Type: Application
    Filed: December 10, 2007
    Publication date: October 2, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Sumihiro Ichikawa, Koji Takei, Noriyoshi Shimizu, Yasunari Suzuki, Ryo Fukasawa, Daisuke Matono, Yuichiro Shimizu
  • Publication number: 20060160340
    Abstract: A method and apparatus for processing a thin film able to easily form grooves in a conductive thin film on an insulating substrate, comprising bringing a first electrode into contact with the conductive thin film, maintaining a conductive state between a tip of a second electrode with a voltage applied with respect to the first electrode and the surface of the conductive thin film, and using the tip of the second electrode to scan the conductive thin film so as to thereby form grooves passing through the thickness of the conductive thin film and exposing the surface of the insulating substrate at their bottoms in the conductive thin film.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 20, 2006
    Inventors: Koji Takei, Sumihiro Ichikawa, Yasunari Suzuki, Ryo Fukasawa, Daisuke Matono
  • Patent number: 6307148
    Abstract: An indium layer and a copper layer, and whenever necessary, a gallium layer or a gallium-alloy layer, are laminated on an electrode film formed on one of the surfaces of a substrate to form a metallic film. The metallic film is then subjected to sulfurization treatment or selenization treatment to form a p-type semiconductor layer made of “CuInS2 or CuInSe2” or “Cu(In, Ga)S2 or Cu(In, Ga)Se2”. This p-type semiconductor layer is subjected to KCN treatment, for removing impurities such as copper sulfide, copper selenide, etc., by a KCN solution, and an n-type semiconductor layer is formed on this p-type semiconductor layer to form a solar cell. In this instance, the indium layer is formed under heating, or is heat-treated by heat-treatment while the surface of the indium layer is exposed.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: October 23, 2001
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kenji Takeuchi, Yoshio Onuma, Sumihiro Ichikawa