Abstract: A geared electric motor 1 used for power window apparatuses, for example, which is provided with an mature 7 having an armature shaft 7a, an output shaft 8 connected with the armature shaft 7a through a worm gear pair (7a7 and 17) and two friction plates 9 and 10 to be in contact with both end faces of the armature shaft 7a. The armature shaft 7a of this motor 1 is prevented from rotation by frictional resistance generating between the friction plates 9, 10 and the armature shaft 7a even if the output shaft 8 is applied with rotatory force.

Abstract: An electric motor is provided with especially brushes of which rear ends are cut diagonally to form acute angles at the corner edges on the backward side of the rotating direction of the armature. The brushes are maintained securely in brush holders without vibration by first and second side walls of the brush holders according to component force of pressing force applied on the slant rear ends of the brushes by pressing members, therefore the objectionable noise caused by the "stick-slip" is prevented very effectively without introducing complicated structure in the motor.

Abstract: An electric motor is provided with a breather, which is made of elastic material such as rubber and provided with three triangular tongues protruding in the longitudinal direction of a tubular shaped breather body around about an aperture opening in the outside air. According to this invention, formation of waterdrops and membranous water is hindered in the aperture of the breather, and water penetration into the electric motor is prevented effectively.

Abstract: A memory control system comprises a memory unit including a plurality of chips each having a shift register type memory having a plurality of information loops, the number of chips being larger than a predetermined number, the predetermined number of bits out of those bits which are read from or written into the information loops of the respective chips at the same timing constituting a unit information; and an additional memory which stores information indicative of normal loop condition or defective loop condition for each of the information loops in each of the chips and information indicative of whether the number of normal loops in each information loop group corresponding to the bits which are read or written at the same timing is larger than said predetermined number or not.