Abstract: A memory access control apparatus includes an address detecting (CAQ) circuit for detecting a real address at which read data has been stored, and a correspondence storing circuit (CAT) for storing a correspondence between a real address and a logical address. A control circuit (IMC) is also provided for controlling a writing operation in such a way that, at a real address detected by the address detecting circuit, a next transfer unit of data is written, after the transfer unit of data previously stored at the real address has been read, by specifying the corresponding logical address. Thus, a continuous reading can be effected without stopping due to a writing operation.