Abstract: Provided is an identification information generation device capable of generating identification information with its complete individual identifiability guaranteed.

Abstract: A signature generation apparatus includes basic operation execution units each executing a basic operation included in a signature generation procedure; and a whole operation controller connected to the basic operation execution units to control operations in the basic operation execution units and monitor operation states of the basic operation execution units, in which when there is a basic operation execution unit among the basic operation execution units which is executing a secret operation which uses data to be concealed as an argument, the whole operation controller causes basic operation execution units other than the basic operation execution unit to simultaneously execute a random number operation which uses a random number originally used for signature generation as an argument.

Abstract: Provided is an identification information generation device capable of generating identification information with its complete individual identifiability guaranteed.

Abstract: A plurality of group signature processes is executed in parallel with a small number of processing devices and small power consumption, without lowering an average response speed. A signature processing device includes subsystems for each type of basic operations included in a signature processing procedure. Each subsystem has a configuration in which one or more basic operation execution units and a dispatcher that monitors operation states thereof and instructs to execute an operation are interconnected. A plurality of signature generation requests or signature verification requests is accepted as a single input, and a plurality of requests is simultaneously processed in parallel. At this time, each subsystem assigns operations in different requests to unoccupied basic operation units and causes the basic operation units to simultaneously execute the operations, without being occupied with a single request.

Abstract: A signature generation apparatus (1) includes basic operation execution units (2)-(6) each executing a basic operation included in a signature generation procedure; and a whole operation controller (7) connected to the basic operation execution units (2)-(6) to control operations in the basic operation execution units (2)-(6) and monitor operation states of the basic operation execution units (2)-(6), in which when there is a basic operation execution unit among the basic operation execution units (2)-(6) which is executing a secret operation which uses data to be concealed as an argument, the whole operation controller (7) causes other basic operation execution units than the basic operation execution unit to simultaneously execute a random number operation which uses a random number as an argument.

Abstract: A signature generation apparatus generates a signature for a message m from the i-th user, and computes any two or three of a[1]?[x] (mod n), a[2]?[s] (mod n), and w?[t] (mod l) are in parallel. For this reason, the signature generation apparatus is provided with a plurality of fast arithmetic units (sub-IPs) within the IP core. The individual sub-IPs are connected to each other via a narrow-band, single-layer local bus.

Abstract: The present invention is directed to an information processing system composed of plural information processing units adapted for mutually executing data communication, and for executing data processing in which communication data has been applied. The first entity A transmits error notification data on the basis of error detection to execute initial state return processing on the condition that data reception after error notification data has been transmitted is made, and the second entity B transmits error notification data on the basis of error detection to execute initial state return processing on the condition that transmit processing of error notification data is executed. Thus, the both entities A and B can return to the initial state in a manner synchronous with each other. As a result, it becomes possible to perform reliable error recovery and data processing restart.

Abstract: A signature generation apparatus generates a signature for a message m from the i-th user, and computes any two or three of a[1]?[x](mod n), a[2]?[s](mod n), and w?[t](mod l) are in parallel. For this reason, the signature generation apparatus is provided with a plurality of fast arithmetic units (sub-IPs) within the IP core. The individual sub-IPs are connected to each other via a narrow-band, single-layer local bus.

Abstract: To provide a high-speed combinational circuit including an S-Box and a method for creating an RO-BDD that defines a configuration of the combinational circuit. The combinational circuit includes a number of independent selector groups for each generating an output bit separately, the number corresponding to number of the output bits, and a driver chain for supplying a primary input to each of the selector groups, in which each of the selector groups includes a plurality of selectors connected to each other to form a number of stages, the number of stages being equal to or less than number of bits of the primary input, and a select signal for the selectors in each stage is driven by one primary input.

Abstract: The present invention is directed to an information processing system composed of plural information processing units adapted for mutually executing data communication, and for executing data processing in which communication data has been applied. The first entity A transmits error notification data on the basis of error detection to execute initial state return processing on the condition that data reception after error notification data has been transmitted is made, and the second entity B transmits error notification data on the basis of error detection to execute initial state return processing on the condition that transmit processing of error notification data is executed. Thus, the both entities A and B can return to the initial state in a manner synchronous with each other. As a result, it becomes possible to perform reliable error recovery and data processing restart.

Abstract: A data processing apparatus that tests whether a secure circuit is normal or not while maintaining confidentiality of the secured circuit is provided: wherein the secured circuit conducts a self-diagnostic test thereof in accordance with a self-diagnostic test start instruction signal from a CPU, and the secured circuit outputs a self-diagnostic test result signal indicating whether the secured circuit is normal or not to the CPU.

Abstract: A signal processing method for a digital signal comprising the steps of: establishing a Yule-Walker equation having the following form by using a matrix that includes, as components, the elements of a Galois field GF(2m), and a vector that includes, as components, the elements of the Galois field GF(2m) ( S 0 S 1 ? S l - 1 S 1 S 2 ? S l ? ? ? S l - 1 S l ? S 2 ? l - 2 ) ? ( ? l ( l ) ? ? ? 1 ( l ) ) = ( S l ? ? S 2 ? l - 1 ) ; employing Jacobi's formula to obtain the solution of the above equation by the calculation of determination of symmetric matrices; determining the number of errors to be the maximum matrix size that corresponds to the obtained solution that is not zero; and determining whether the number of errors equals the maximum number of correctable errors.

Abstract: A data processing apparatus capable of testing whether a secure circuit is normal or not while maintaining confidentiality of the secured circuit is provided: wherein the secured circuit conducts a self-diagnostic test thereof in accordance with a self-diagnostic test start instruction signal from a CPU, and the secured circuit outputs a self-diagnostic test result signal indicating whether the secured circuit is normal or not to the CPU.

Abstract: A combinational circuit comprises: a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2m) (m is an integer equal to or greater than 2), wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. Further, according to the present invention, these multipliers each include an adder connected between an AND calculator and an output side XOR calculator, wherein the output side XOR calculator is used in common, and wherein the outputs of the AND calculators in the multipliers are added by the adders, and the addition results are calculated by the output side XOR calculator that is used in common.

Abstract: A decoding circuit used to correct an error in a digital signal includes: an input unit for entering coded digital signals ID in parallel in accordance with the number of interleaved codes; a processor including an error locator polynomial calculator and an error value polynomial calculator for processing data obtained serially from the interleaved codes that are received by the input unit; and an output unit for correcting errors by employing the output data that are received from the processor and the digital signals ID, and for outputting in parallel the obtained digital signals OD, for which an error has been corrected by a linear calculation on a Galois field, in accordance with the number of interleaved codes.

Abstract: A multiplication module, including a first input unit and a second input unit, for multiplying m bits of data in a Galois field GF(2m)(m?1), includes: first and second power arithmetic units for receiving the first m bits of data from the first input unit; a first multiplication unit for receiving the first m bits of data and the output of the first power arithmetic unit; a second multiplication unit for receiving second m bits of data from the second input unit and the output of the second power arithmetic unit; a selection unit for receiving an output signal from the second multiplication unit and the second m bits of data; and a control unit for outputting a control signal to the first power arithmetic unit, the second arithmetic unit and the selection unit, wherein the first power arithmetic unit receives a first control signal, the second power arithmetic unit receives a second control signal, and the selection unit receives a third control signal, for controlling the output of the selection unit, while

Abstract: A data storage device includes an encryption circuit for encrypting desired data and personal identification information by use of an encryption key created out of a given piece of the personal identification information such as a password, a magnetic disk for recording the data and the personal identification information which are encrypted by the encryption circuit, and a central processing unit for executing user verification by use of the encrypted personal identification information stored in the magnetic disk. The user verification is executed based on such verification data. The write data transmitted from a host system are encrypted by use of the foregoing encryption key and are recorded in the magnetic disk. Alternatively, the data read out of the magnetic disk are decrypted by use of the encryption key and are transmitted to the host system.

Abstract: A system having multiple encoders of different maximum error correction capability, which reduces the entire size of the system by allowing most of the system to be shared among these encoders. This is accomplished by using an encoder that is capable of calculating parities of 2 or more kinds of bit numbers with different error correction capability. The system includes a circuit that generates a modified word by assigning a predetermined value to input an information word; and a circuit that generates an intermediate signal “u” by a linear operation using a modified word and matrix “P”. These circuits are combined with linear operation circuits for generating value of parity p1, . . . , p&agr;, each of whose bit number is different, by a linear operation using all or part of the intermediate signal and matrixes Q1, . . . , Q&agr; respectively.

Abstract: To provide a high-speed combinational circuit including an S-Box and a method for creating an RO-BDD that defines a configuration of the combinational circuit. The combinational circuit includes a number of independent selector groups for each generating an output bit separately, the number corresponding to number of the output bits, and a driver chain for supplying a primary input to each of the selector groups, in which each of the selector groups includes a plurality of selectors connected to each other to form a number of stages, the number of stages being equal to or less than number of bits of the primary input, and a select signal for the selectors in each stage is driven by one primary input.

Abstract: A combinational circuit comprises: a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2m) (m is an integer equal to or greater than 2), wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. Further, according to the present invention, these multipliers each include an adder connected between an AND calculator and an output side XOR calculator, wherein the output side XOR calculator is used in common, and wherein the outputs of the AND calculators in the multipliers are added by the adders, and the addition results are calculated by the output side XOR calculator that is used in common.