Abstract: A wiring substrate is configured such that a build-up layer is formed only on a front surface (a single side) of a core substrate and such that the distance between a semiconductor device mounted on the front surface thereof and an electronic component mounted on the back surface thereof or incorporated therein behind the back surface is reduced to thereby enhance electrical characteristics of an electrically continuous path therebetween, and whose overall strength is enhanced so as not to be prone to deflection or warpage. The wiring substrate includes a relatively thin first core substrate 2 having a front surface 3 and a back surface 4; a relatively thick second core substrate 6 superposed on the back surface 4 of the first core substrate 2 and having a through opening 9 formed therein, the first substrate 2 and the through opening 9 defining a recess 9; and a build-up layer BU formed on the front surface 3 of the first core substrate 2 and including wiring layers 16 and 25 and dielectric layers 23 and 26.

Abstract: The wiring board 1 is provided with the first resin insulating layer 7, the first filled via 19 penetrating it and filled and formed by the plating, and the second conductor layer 29 formed by the plating on them. In them, the second conductor layer 29 comprises the first resin insulating layer 7, the electroless plating layer 33 formed on the first filled via 19, and the electrolytic plating layer 37 composed of plating particle of substantially uniform size, formed thereon.

Abstract: A wiring substrate is configured such that a build-up layer is formed only on a front surface (a single side) of a core substrate and such that the distance between a semiconductor device mounted on the front surface thereof and an electronic component mounted on the back surface thereof or incorporated therein behind the back surface is reduced to thereby enhance electrical characteristics of an electrically continuous path therebetween, and whose overall strength is enhanced so as not to be prone to deflection or warpage. The wiring substrate includes a relatively thin first core substrate 2 having a front surface 3 and a back surface 4; a relatively thick second core substrate 6 superposed on the back surface 4 of the first core substrate 2 and having a through opening 9 formed therein, the first substrate 2 and the through opening 9 defining a recess 9; and a build-up layer BU formed on the front surface 3 of the first core substrate 2 and including wiring layers 16 and 25 and dielectric layers 23 and 26.

Abstract: The wiring board 1 is provided with the first resin insulating layer 7, the first filled via 19 penetrating it and filled and formed by the plating, and the second conductor layer 29 formed by the plating on them. In them, the second conductor layer 29 comprises the first resin insulating layer 7, the electroless plating layer 33 formed on the first filled via 19, and the electrolytic plating layer 37 composed of plating particle of substantially uniform size, formed thereon.

Abstract: Undesirable deposition of polyoxymethylene onto the inner wall of a polymerization reactor and onto a stirrer, which deposition is observed in the slurry polymerization of formaldehyde carried out in an inert organic liquid medium, can be minimized by carrying out the slurry polymerization in the presence of a polymerization catalyst prepared by bringing a metal chelate compound into contact with polyoxymethylene in an inert organic liquid medium in the presence of formaldehyde. Preferably, the slurry polymerization is carried out in the presence of, in addition to the above-mentioned polymerization catalyst, at least one polyvalent metal salt of an alkylsalicylic acid or of a dialkyl ester of sulfosuccinic acid. It is also preferable to use a tubular closed loop reactor equipped with an impeller wherein gaseous formaldehyde is blown into the reactor in a position located downstream from the impeller, while the catalyst-containing slurry is circulated therethrough.