Abstract: A nonvolatile read only memory detects a time varying change of the amount of data written in the memory cell transistor using a circuit for supplying a constant potential which is higher than the threshold voltage of a reference cell transistor and which is independent of a power source voltage used for reading out connected to the gate of the reference cell transistor.

Abstract: An address selection device comprising an address buffer for receiving an address selection signal to produce an output signal which is complementary to the address selection signal; and a decoder circuit for decoding the address selection signal which includes a plurality of MOS transistors connected in parallel with one another and for receiving at their gates corresponding address bit signals of the address selection signal, a MOS transistor as a load resistor connected in series with said plurality of MOS transistors, and a MOS transistor connected between the load resistor MOS transistor and a power source terminal for operating a power source switch and for receiving at the gate a specified bit signal of the complementary signal applied from the address buffer.

Abstract: Disclosed is a metal oxide semiconductor integrated circuit device having an array of electrically rewritable, insulated gate type non-volatile semiconductor memory cells formed on a semiconductor substrate, read/write mode setting circuit and address designating circuits arranged corresponding to the memory cell array, those circuits being fabricated on the substrate, and a field insulating layer formed on the substrate. A cut portion is formed in the field insulating layer to surround the memory cell array.