Abstract: An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.

Abstract: An integrated circuit memory device includes a test mode. Data is written to and read from the integrated circuit memory device in the test mode. The integrated circuit memory device includes a memory array that includes memory cells that store data. A test control circuit generates control signals that control the data read from the memory cells. A data output circuit outputs data read from the memory cells from the integrated circuit memory device in response to the test column address strobe signal. In particular, the test column address strobe signal includes a series of high to low and low to high transitions, wherein the data output circuit outputs data read from the memory cells in response to the series of high to low and low to high transitions.

Abstract: Current control systems and methods are provided for a plurality of integrated circuit devices that are commonly attached to a bus, including a plurality of signal lines. Each integrated circuit includes a plurality of output drivers, a respective one of which drives a respective one of the plurality of signal lines. Each integrated circuit includes a current setting circuit that sets an output current for each of the output drivers in the integrated circuit. A controlling circuit controls the current setting circuit in each integrated circuit, such that each current setting circuit simultaneously sets an output current for an output driver corresponding to a different one of the plurality of signal lines.