Abstract: An apparatus, system and other techniques for a smart card device, one or more host devices and a modular computing system comprising a smart card device and one or more host devices are described. For example, an apparatus or example smart card device may comprise one or more processor circuits, an interface coupled to the one or more processor circuits, the smart card device sized to be removably inserted into a host device and the interface configured to removably couple the smart card device to the host device, and logic, at least a portion of which is in hardware, the logic to configure the smart card device based on one or more characteristics of the host device. Other embodiments are described and claimed.

Abstract: In accordance with some embodiments, raw data in a first data format may be generated or received. Then, the raw data may be transformed to cloud data in a second data format. Finally, the cloud data may be transformed into device data in a third data format.

Abstract: Identifying at least one unresolved symbol referenced in a first program component during a compilation phase of the first program component, searching a second program component that comprises object code, for a definition of the unresolved symbol, and selecting a type of compiler optimization for at least the first program component based at least in part on the results of the search of the second program component.

Abstract: A method, system, and computer program product for performing register promotion, that optimizes placement of load and store operations of a computer program within a compiler. Based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location, the system is an approach to register promotion that models the optimization as two separate problems: (1) the partial redundancy elimination (PRE) of loads and (2) the PRE of stores. Both of these problems are solved through a sparse approach to PRE. The static single assignment PRE (SSAPRE) method for eliminating partial redundancy using a sparse SSA representation representations the foundation in eliminating redundancy among memory accesses, enabling the achievement of both computational and live range optimality in register promotion results.

Abstract: A system and method of eliminating some of the indirect addressing associated with Position Independent Code (PIC). The invention applies cross-module optimization to dynamic linking of shared libraries. A definition table is built that defines where each symbol within an application program and associated shared library is defined. Also stored in the definitions table is an associated attribute. The definition table is utilized to eliminate indirect addressing wherever possible. As a result, overall system performance is increased.

Abstract: In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.

Abstract: A system and method for optimizing a source code representation comprising a plurality of basic blocks are described. The optimized source code representation is to be executed in a target machine. The system operates by selecting from the source code representation a basic block pair comprising a source basic block and one or more target basic blocks. An instruction in the source basic block is identified that can be moved from the source basic block to the target basic block(s) while preserving program semantics. Either the instruction or a representation of the instruction is moved from the source basic block to the target basic block(s) as a function of resource utilization of the target machine that would result from this movement.

Abstract: A system and method of generating object code from an intermediate representation of source code is described. The intermediate representation includes a plurality of basic blocks each being represented by a plurality dam dependency graphs, wherein each data dependency graph comprises a plurality of nodes each corresponding to an instruction from the target computer instruction set. The present invention operates by selecting a source basic block (that is one of the basic blocks of the intermediate representation) and a target basic block (that is another of the basic blocks of the intermediate representation), and by identifying a maximal set of instructions contained in the source basic block that are movable from the source basic block to the target basic block without violating any data dependency relationships of the data dependency graphs. An overall cost model of aggregately moving instructions of the maximal set from the source basic block to the target basic block is generated.