Patents by Inventor Sun-Hye Shin
Sun-Hye Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10102900Abstract: A semiconductor device may include a word line selector configured to generate an active signal for selecting a word line, based on a row address. The active signal may be divided into a read active signal generated based on a read command and a write active signal generated based on a write command.Type: GrantFiled: May 2, 2017Date of Patent: October 16, 2018Assignee: SK hynix Inc.Inventor: Sun Hye Shin
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Publication number: 20180144789Abstract: A semiconductor device may be provided. The semiconductor device may include a word line selector configured to generate an active signal for selecting a word line, based on a row address. The active signal may be divided into a read active signal generated based on a read command and a write active signal generated based on a write command.Type: ApplicationFiled: May 2, 2017Publication date: May 24, 2018Applicant: SK hynix Inc.Inventor: Sun Hye SHIN
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Patent number: 9842641Abstract: A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.Type: GrantFiled: March 27, 2017Date of Patent: December 12, 2017Assignee: SK Hynix Inc.Inventors: Sun-Hye Shin, Nak-Kyu Park
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Patent number: 9741425Abstract: A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank.Type: GrantFiled: April 24, 2015Date of Patent: August 22, 2017Assignee: SK Hynix Inc.Inventors: Sun-Hye Shin, Nak-Kyu Park
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Publication number: 20170200488Abstract: A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Inventors: Sun-Hye SHIN, Nak-Kyu PARK
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Patent number: 9640245Abstract: A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.Type: GrantFiled: July 13, 2015Date of Patent: May 2, 2017Assignee: SK Hynix Inc.Inventors: Sun-Hye Shin, Nak-Kyu Park
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Patent number: 9530471Abstract: A semiconductor memory apparatus may include a driving voltage-applying unit and a sub-word line-driving unit. The driving voltage-applying unit may be configured to generate a driving voltage in response to an active signal, a word line-enabling signal and a sub-word line selection signal. The sub-word line-driving unit may be configured to drive a sub-word line as a voltage level of the driving voltage in response to a main word line and the sub-word line selection signal.Type: GrantFiled: October 23, 2015Date of Patent: December 27, 2016Assignee: SK HYNIX INC.Inventor: Sun Hye Shin
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Publication number: 20160372172Abstract: A semiconductor memory apparatus may include a driving voltage-applying unit and a sub-word line-driving unit. The driving voltage-applying unit may be configured to generate a driving voltage in response to an active signal, a word line-enabling signal and a sub-word line selection signal. The sub-word line-driving unit may be configured to drive a sub-word line as a voltage level of the driving voltage in response to a main word line and the sub-word line selection signal.Type: ApplicationFiled: October 23, 2015Publication date: December 22, 2016Inventor: Sun Hye SHIN
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Publication number: 20160232961Abstract: A semiconductor memory device includes a plurality of memory cell blocks each including a plurality of word lines and suitable for being selectively activated based on an active command and a row address, wherein word lines are selected from the respective activated memory cell blocks based on the active command and the row address, and a column decoding block sequentially accessing the activated memory cell blocks to input/output data thereof by decoding a column address based on the row address.Type: ApplicationFiled: July 13, 2015Publication date: August 11, 2016Inventors: Sun-Hye SHIN, Nak-Kyu PARK
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Publication number: 20160155490Abstract: A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank.Type: ApplicationFiled: April 24, 2015Publication date: June 2, 2016Inventors: Sun-Hye SHIN, Nak-Kyu PARK
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Patent number: 8482995Abstract: A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.Type: GrantFiled: October 7, 2011Date of Patent: July 9, 2013Assignee: Hynix Semiconductor Inc.Inventors: Sun-Hye Shin, Sung-Joo Ha
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Publication number: 20120026814Abstract: A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.Type: ApplicationFiled: October 7, 2011Publication date: February 2, 2012Inventors: Sun-Hye Shin, Sung-Joo Ha
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Patent number: 8036050Abstract: A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.Type: GrantFiled: December 17, 2008Date of Patent: October 11, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sun-Hye Shin, Sung-Joo Ha
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Patent number: 7859924Abstract: Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and second bank groups and then outputs data to the pads from the other of the first and second bank groups.Type: GrantFiled: December 22, 2006Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Seong Hwi Song, Sun Hye Shin
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Publication number: 20100056066Abstract: A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.Type: ApplicationFiled: December 17, 2008Publication date: March 4, 2010Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Sun-Hye SHIN, Sung-Joo Ha
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Patent number: 7636266Abstract: A semiconductor memory apparatus includes a write driver that receives a reset signal, a write enable signal, and a data signal, and transmits data, which is input from the data signal, to an input/output (IO) line when the write enable signal is applied, and an overdrive unit that is connected to the IO line of the write driver and outputs a voltage larger than a driving voltage of the write driver when the write driver outputs a high level.Type: GrantFiled: December 29, 2006Date of Patent: December 22, 2009Assignee: Hynix Semiconductor Inc.Inventor: Sun Hye Shin
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Patent number: 7492646Abstract: An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.Type: GrantFiled: March 14, 2007Date of Patent: February 17, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jong-Chern Lee, Sun-Hye Shin
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Publication number: 20080002510Abstract: A semiconductor memory apparatus includes a write driver that receives a reset signal, a write enable signal, and a data signal, and transmits data, which is input from the data signal, to an input/output (IO) line when the write enable signal is applied, and an overdrive unit that is connected to the IO line of the write driver and outputs a voltage larger than a driving voltage of the write driver when the write driver outputs a high level.Type: ApplicationFiled: December 29, 2006Publication date: January 3, 2008Applicant: Hynix Semiconductor Inc.Inventor: Sun Hye Shin
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Publication number: 20080001582Abstract: An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.Type: ApplicationFiled: March 14, 2007Publication date: January 3, 2008Inventors: Jong-Chern Lee, Sun-Hye Shin
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Publication number: 20070211546Abstract: Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and second bank groups and then outputs data to the pads from the other of the first and second bank groups.Type: ApplicationFiled: December 22, 2006Publication date: September 13, 2007Applicant: Hynix Semiconductor Inc.Inventors: Seong Hwi Song, Sun Hye Shin