Patents by Inventor Sun-Hyuck Yon

Sun-Hyuck Yon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistance variable memory apparatus, read circuit unit and operation method therefor
    Patent number: 9449685
    Abstract: A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (ADC) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell array.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 20, 2016
    Assignee: SK hynix Inc.
    Inventor: Sun Hyuck Yon
  • RESISTANCE VARIABLE MEMORY APPARATUS, READ CIRCUIT UNIT AND OPERATION METHOD THEREFOR
    Publication number: 20160141027
    Abstract: A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (ADC) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell to array.
    Type: Application
    Filed: March 18, 2015
    Publication date: May 19, 2016
    Inventor: Sun Hyuck YON
  • Variable resistance memory device and operating method thereof
    Patent number: 9030861
    Abstract: An operating method of a variable resistance memory device including a pre-read step which may include the steps of: reading a first reference cell using a first reference voltage; reading a second reference cell using a second reference voltage; and setting a third reference voltage based on the first and second reference voltages; and a main read step of reading a selected memory cell using the third reference voltage.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sun Hyuck Yon
  • Phase change memory device, operation method thereof, and data storage device having the same
    Patent number: 8917544
    Abstract: A phase change memory device includes: a memory cell arranged at a region where a word line and a bit line cross each other; and a control logic including: a program control logic configured to control a program operation of the memory cell; a read control logic configured to control a read operation of the memory cell; and an operation complete signal transfer unit configured to adjust a transfer time point of an operation complete signal transferred between the program control logic and the read control logic.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sun Hyuck Yon, Dong Keun Kim
  • VARIABLE RESISTANCE MEMORY DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20140063904
    Abstract: An operating method of a variable resistance memory device including a pre-read step which may include the steps of: reading a first reference cell using a first reference voltage; reading a second reference cell using a second reference voltage; and setting a third reference voltage based on the first and second reference voltages; and a main read step of reading a selected memory cell using the third reference voltage.
    Type: Application
    Filed: December 19, 2012
    Publication date: March 6, 2014
    Applicant: SK hynix Inc.
    Inventor: Sun Hyuck YON
  • PHASE CHANGE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME
    Publication number: 20130155765
    Abstract: A phase change memory device includes: a memory cell arranged at a region where a word line and a bit line cross each other; and a control logic including: a program control logic configured to control a program operation of the memory cell; a read control logic configured to control a read operation of the memory cell; and an operation complete signal transfer unit configured to adjust a transfer time point of an operation complete signal transferred between the program control logic and the read control logic.
    Type: Application
    Filed: August 22, 2012
    Publication date: June 20, 2013
    Applicant: SK HYNIX INC.
    Inventors: Sun Hyuck YON, Dong Keun KIM
  • PHASE CHANGE MEMORY DEVICE AND DATA STORAGE DEVICE HAVING THE SAME
    Publication number: 20130135923
    Abstract: A phase change memory device includes a memory cell array including a plurality of memory cells each arranged at a region where a word line and a bit line cross each other, and a control logic including a reset program control logic configured to control a reset program operation for the plurality of memory cells and a set program control logic configured to control a set program operation for the plurality of memory cells.
    Type: Application
    Filed: August 30, 2012
    Publication date: May 30, 2013
    Applicant: SK HYNIX INC.
    Inventor: Sun Hyuck YON
  • Semiconductor memory device and operation method thereof
    Patent number: 8331190
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun-Hyuck Yon, Kee-Teok Park
  • SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF
    Publication number: 20110255356
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Inventors: Sun-Hyuck Yon, Kee-Teok Park
  • Semiconductor memory device and operation method thereof
    Patent number: 7995416
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun-Hyuck Yon, Kee-Teok Park
  • Delay apparatus for delay locked loop
    Patent number: 7710178
    Abstract: A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconductor memory apparatus from an output terminal of the delay locked loop. At least one of the plurality of delay devices is composed of a variable delay device in which a delay time varies according to a change in operation voltage.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: May 4, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sun-Hyuck Yon
  • SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF
    Publication number: 20090168584
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Sun-Hyuck YON, Kee-Teok Park
  • Delay apparatus for delay locked loop
    Publication number: 20080136477
    Abstract: A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconductor memory apparatus from an output terminal of the delay locked loop. At least one of the plurality of delay devices is composed of a variable delay device in which a delay time varies according to a change in operation voltage.
    Type: Application
    Filed: June 28, 2007
    Publication date: June 12, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Sun Hyuck Yon