Patents by Inventor Sunay Shah

Sunay Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8976099
    Abstract: A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors (8,10) are provided for selectively isolating the charge storage node from a first voltage input (9,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (10). The first transistor forms part of the voltage follower circuit.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: March 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Sunay Shah, Patrick Zebedee, Benjamin James Hadwen, Michael James Brownlow
  • Patent number: 8330093
    Abstract: An ambient light sensor includes a first stack of at least two photodiodes, wherein a cathode of one of the at least two photodiodes is electrically connected to an anode of another of the at least two photodiodes. The ALS further includes a bias source for providing a bias voltage to the first stack, and at least one switch electrically connected to the first stack. The at least one switch is operative to periodically apply the bias voltage to and remove the bias voltage from the first diode stack.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: December 11, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michael P. Coulson, Hajime Washio, Benjamin J. Hadwen, Sunay Shah
  • Patent number: 8194197
    Abstract: A display device includes a first layer having an optically active display portion, a second layer including a photovoltaic element, and a third layer including electronics operatively coupled to the first layer, wherein the electronics are configured to drive the optically active display portion. Further, the second layer is arranged between the first and third layers.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: June 5, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Allan Evans, Stephen Day, Sunay Shah, Patrick Zebedee, Lesley Parry-Jones, Gareth Nicholas
  • Publication number: 20120061802
    Abstract: A bipolar junction transistor includes a semiconductor island on an insulating substrate; an emitter and at least one of a collector and sub collector within the semiconductor island, the emitter and the at least one of the collector and the sub collector being of a first conductivity type; a base within the semiconductor island separating the emitter and the at least one of the collector and the sub collector, the base being of a second conductivity type; a base contact region within the semiconductor island, the base contact region being of the second conductivity type; and a connecting base region adjacent the base within the semiconductor island and connecting the base to the base contact region while not directly contacting the emitter, the connecting base region being of the second conductivity type with a doping concentration less than a doping concentration of the base contact region.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 15, 2012
    Inventors: Gareth NICHOLAS, Benjamin James Hadwen, Sunay Shah
  • Publication number: 20120038597
    Abstract: A display device includes a liquid crystal display having a plurality of pixels, each pixel having a corresponding pixel electrode. Each pixel also includes a volatile memory (VM) cell and a non-volatile memory (NVM) cell. The VM cell includes a VM cell input for receiving data to be stored in the VM cell and a VM cell output for outputting data stored in the VM cell. The NVM cell includes an NVM program input operatively coupled to the VM cell output, and an NVM data output for providing data stored in the first NVM cell to the pixel electrode. The display device also includes programming logic operatively coupled to each of the plurality of pixels, wherein the programming logic is configured to substantially simultaneously program each pixel's first NVM cell with data provided by each pixel's VM cell.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 16, 2012
    Inventors: Michael P. COULSON, Sunay Shah, Benjamin J. Hadwen
  • Publication number: 20110298531
    Abstract: A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors (8,10) are provided for selectively isolating the charge storage node from a first voltage input (9,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (10). The first transistor forms part of the voltage follower circuit.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 8, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Sunay SHAH, Patrick ZEBEDEE, Benjamin James HADWEN, Michael James BROWNLOW
  • Publication number: 20110249219
    Abstract: A display device includes a first layer having an optically active display portion, a second layer including a photovoltaic element, and a third layer including electronics operatively coupled to the first layer, wherein the electronics are configured to drive the optically active display portion. Further, the second layer is arranged between the first and third layers.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 13, 2011
    Inventors: Allan EVANS, Stephen Day, Sunay Shah, Patrick Zebedee, Lesley Parry-Jones, Gareth Nicholas
  • Publication number: 20110151928
    Abstract: An apparatus for acquiring an image comprises a display (60), such as an LCD and backlight, for illuminating the object. A photosensor array (61) detects light reflected from the object. A controller (62) causes the display (60) and the photosensor array (61) to: illuminate the object (100); acquire (102) a first image (104) of the object; display a first illuminating pattern (106) for illuminating the object, which first illuminating pattern is derived (108) from the first image; and acquire (102) a second image (110) of the object illuminated by the first illuminating pattern (106). The controller (62) preferably causes the display (60) and the photosensor array (61) to: display a second illuminating pattern (112) for illuminating the object, which second illuminating pattern is derived (108) from at least the second image; and acquire a third image (114) of the object illuminated by the second illuminating pattern (112).
    Type: Application
    Filed: August 4, 2009
    Publication date: June 23, 2011
    Inventors: David James Montgomery, Benjamin James Hadwen, Sunay Shah, Tamas Zeffer
  • Publication number: 20110114824
    Abstract: An ambient light sensor includes a first stack of at least two photodiodes, wherein a cathode of one of the at least two photodiodes is electrically connected to an anode of another of the at least two photodiodes. The ALS further includes a bias source for providing a bias voltage to the first stack, and at least one switch electrically connected to the first stack. The at least one switch is operative to periodically apply the bias voltage to and remove the bias voltage from the first diode stack.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 19, 2011
    Inventors: Michael P. Coulson, Hajime Washio, Benjamin J. Hadwen, Sunay Shah
  • Publication number: 20110012125
    Abstract: A thin film transistor is formed in a semiconductor island on an insulating substrate. The transistor comprises a source (1502) and a drain (1504) of first conductivity type and a channel (1508) of a second opposite conductivity type. The channel is overlapped by one or more insulated gates (1510) and is provided with isolation diodes. Each isolation diode comprises a first region (1506) which is lightly doped and a second region (1512) which is heavily doped and of the second conductivity type. The diodes are not overlapped by the gate (1510). The first and second regions (1506, 1512) extend away from the channel (1508) by less than the length of the adjacent source or drain.
    Type: Application
    Filed: April 20, 2009
    Publication date: January 20, 2011
    Inventors: Gareth Nicholas, Benjamin James Hadwen, Sunay Shah
  • Publication number: 20100182207
    Abstract: In an antenna device of this invention, an antenna (81) and electric wiring connecting the antenna (81) with a receiving section (82) are monolithically formed on an active matrix substrate through a thin film process. A material of which the antenna (81) is made has a higher electric conductivity than that of a material of which the electric wiring is made.
    Type: Application
    Filed: May 30, 2008
    Publication date: July 22, 2010
    Inventors: Kazuhiko Miyata, Lloyd Lukama, Emmanuel Zyambo, Sunay Shah
  • Patent number: 7529148
    Abstract: A programmable read-only memory comprises a memory cell or a plurality of such cells arranged as an array. Each memory cell comprises a transistor, such as a MOS TFT. An electronic switch allows the control electrode, such as the gate, to be substantially electrically isolated during a programming mode so that the gate is electrically floating during this mode. During the programming mode, a programming voltage is supplied across the main conductive path of the transistor, such as across the source-drain channel. The programming voltage is sufficiently large to fuse the main conduction path when the control electrode of the transistor is floating but is insufficient to fuse the main conduction path when the control electrode is not floating and is connected to a suitable defined voltage.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: May 5, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Sunay Shah, Olivier Karim Abed-meraim, Patrick Zebedee
  • Publication number: 20070242495
    Abstract: A programmable read-only memory comprises a memory cell or a plurality of such cells arranged as an array. Each memory cell comprises a transistor, such as a MOS TFT. An electronic switch allows the control electrode, such as the gate, to be substantially electrically isolated during a programming mode so that the gate is electrically floating during this mode. During the programming mode, a programming voltage is supplied across the main conductive path of the transistor, such as across the source-drain channel. The programming voltage is sufficiently large to fuse the main conduction path when the control electrode of the transistor is floating but is insufficient to fuse the main conduction path when the control electrode is not floating and is connected to a suitable defined voltage.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 18, 2007
    Inventors: Sunay SHAH, Olivier Karim Abed-meraim, Patrick Zebedee