Patents by Inventor Sundar S. Chetlur

Sundar S. Chetlur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6693434
    Abstract: An automated system for, and method of estimating ring oscillator reliability and testing AC response of a device under test (DUT). In one embodiment, the system includes: (1) a DUT board that accepts, and allows electrical communication with, a plurality of DUTs, (2) a power source, couplable to the DUT board, that provides AC power of controllable characteristics to the plurality of DUTs and (3) an automated switching matrix, couplable between the DUT board and a circuit analyzer, that allows the circuit analyzer to analyze ring oscillators and predetermined portions of the plurality of DUTs at predetermined times as the power source provides the power thereto.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: February 17, 2004
    Assignee: Agere Systems, Inc.
    Inventors: Sundar S. Chetlur, Pradip K. Roy, Johathan Z. Zhou
  • Patent number: 6674151
    Abstract: A semiconductor device having trap sites passivated with deuterium has enhanced immunity to hot carrier effects. The trap sites which are passivated with deuterium are encapsulated beneath a barrier film and are therefore resistant to having the deuterium diffuse away from the trap sites during subsequent high temperature processing operations.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: January 6, 2004
    Assignee: Agere Systems Inc.
    Inventors: Sundar S. Chetlur, Pradip K. Roy, Anthony S. Oates, Sidhartha Sen, Jonathan Z-N. Zhou
  • Patent number: 6576521
    Abstract: A NMOSFET semiconductor device is formed having an LDD structure by simultaneous co-implantation of arsenic and phosphorous to form an N− layer. The co-implantation is performed subsequent to the formation of the gate structure and a thin (100 Å-300 Å) gate spacer but prior to the implantation of a highly doped N+ source/drain.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: June 10, 2003
    Assignee: Agere Systems Inc.
    Inventors: Samir Chaudhry, Sundar S. Chetlur, Hem M. Vaidya
  • Patent number: 6391668
    Abstract: The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: May 21, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Carlos M. Chacon, Sundar S. Chetlur, Brian E. Harding, Minesh A. Patel, Pradip K. Roy
  • Publication number: 20010027547
    Abstract: An automated system for, and method of estimating ring oscillator reliability and testing AC response of a device under test (DUT). In one embodiment, the system includes: (1) a DUT board that accepts, and allows electrical communication with, a plurality of DUTs, (2) a power source, couplable to the DUT board, that provides AC power of controllable characteristics to the plurality of DUTs and (3) an automated switching matrix, couplable between the DUT board and a circuit analyzer, that allows the circuit analyzer to analyze ring oscillators and predetermined portions of the plurality of DUTs at predetermined times as the power source provides the power thereto.
    Type: Application
    Filed: January 24, 2001
    Publication date: October 4, 2001
    Inventors: Sundar S. Chetlur, Pradip K. Roy, Johathan Z. Zhou
  • Patent number: 6228748
    Abstract: The present invention provides a method of using a getter layer on a semiconductor substrate having a first metal stack formed thereon to improve metal to metal contact resistance. The method comprises the steps of forming a getter layer, which may be titanium, on the first metal stack, wherein the getter layer has a higher affinity for oxygen or a higher getter capability than the first metal stack, substantially removing the getter layer by exposing the getter layer to radiation, and forming a second metal stack, which in an advantageous embodiment may also be titanium, on the first metal stack.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: May 8, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Steven M. Anderson, Sundar S. Chetlur
  • Patent number: 6187665
    Abstract: A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The process sequence is carried out prior to the introduction of metal conductive films to the device. The process sequence includes a three-step passivation, de-passivation, re-passivation sequence and utilizes a barrier film to encapsulate deuterium molecules in the vicinity of a gate oxide, during the de-passivation operation.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: February 13, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Sundar S. Chetlur, Pradip K. Roy, Anthony S. Oates, Sidhartha Sen, Jonathan Z-N. Zhou
  • Patent number: 5989984
    Abstract: The present invention provides a method of using a getter layer on a semiconductor substrate having a first metal stack formed thereon to improve metal to metal contact resistance. The method comprises the steps of forming a getter layer, which may be titanium, on the first metal stack, wherein the getter layer has a higher affinity for oxygen or a higher getter capability than the first metal stack, substantially removing the getter layer by exposing the getter layer to radiation, and forming a second metal stack, which in an advantageous embodiment may also be titanium, on the first metal stack.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: November 23, 1999
    Assignee: Lucent Technologies, Inc.
    Inventors: Steven M. Anderson, Sundar S. Chetlur