Abstract: An efficiently-transformed digital self-interference canceller, preferably including an FD transformer, a TD transformer, a channel estimator, a composer, and a controller. The canceller can optionally include a channel memory, a predictor, and/or an extender. A method for digital self-interference cancelation, preferably including receiving inputs, transforming the inputs, generating outputs based on the transformed inputs, transforming the outputs, and/or generating a cancellation signal based on the outputs.

Abstract: An efficiently-transformed digital self-interference canceller, preferably including an FD transformer, a TD transformer, a channel estimator, a composer, and a controller. The canceller can optionally include a channel memory, a predictor, and/or an extender. A method for digital self-interference cancelation, preferably including receiving inputs, transforming the inputs, generating outputs based on the transformed inputs, transforming the outputs, and/or generating a cancellation signal based on the outputs.

Abstract: An efficiently-transformed digital self-interference canceller, preferably including an FD transformer, a TD transformer, a channel estimator, a composer, and a controller. The canceller can optionally include a channel memory, a predictor, and/or an extender. A method for digital self-interference cancelation, preferably including receiving inputs, transforming the inputs, generating outputs based on the transformed inputs, transforming the outputs, and/or generating a cancellation signal based on the outputs.

Abstract: An efficiently-transformed digital self-interference canceller, preferably including an FD transformer, a TD transformer, a channel estimator, a composer, and a controller. The canceller can optionally include a channel memory, a predictor, and/or an extender. A method for digital self-interference cancellation, preferably including receiving inputs, transforming the inputs, generating outputs based on the transformed inputs, transforming the outputs, and/or generating a cancellation signal based on the outputs.

Abstract: An efficiently-transformed digital self-interference canceller, preferably including an FD transformer, a TD transformer, a channel estimator, a composer, and a controller. The canceller can optionally include a channel memory, a predictor, and/or an extender. A method for digital self-interference cancelation, preferably including receiving inputs, transforming the inputs, generating outputs based on the transformed inputs, transforming the outputs, and/or generating a cancellation signal based on the outputs.

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.