Abstract: An analog-to-digital conversion system may include an analog-to-digital converter configured to convert an analog input signal into an equivalent digital input signal, a first filtering path configured to filter the equivalent digital input signal to generate a first filtered digital signal, wherein the first filtering path comprises a zero-overshoot monotonic step response filter, a second filtering path configured to filter the equivalent digital input signal to generate a second filtered digital signal, wherein the second filtering path comprises a frequency-selective filter; and a mixer configured to either: (i) select between the first filtered digital signal and the second filtered digital signal in order to generate an output digital signal; or (ii) combine selected proportions of each of the first filtered digital signal and the second filtered digital signal in order to generate the output digital signal.

Abstract: An analog-to-digital conversion system may include an analog-to-digital converter configured to convert an analog input signal into an equivalent digital input signal, a first filtering path configured to filter the equivalent digital input signal to generate a first filtered digital signal, wherein the first filtering path comprises a zero-overshoot monotonic step response filter, a second filtering path configured to filter the equivalent digital input signal to generate a second filtered digital signal, wherein the second filtering path comprises a frequency-selective filter; and a mixer configured to either: (i) select between the first filtered digital signal and the second filtered digital signal in order to generate an output digital signal; or (ii) combine selected proportions of each of the first filtered digital signal and the second filtered digital signal in order to generate the output digital signal.

Abstract: In accordance with embodiments of the present disclosure, a system may include a digital correcting network for correcting for an intrinsic highpass filter of a microelectromechanical systems (MEMS) microphone such that a combined phase and magnitude response of a cascade of the intrinsic highpass filter and the digital correcting network substantially approximates the response of a target highpass filter.

Abstract: In accordance with embodiments of the present disclosure, a system may include a digital correcting network for correcting for an intrinsic highpass filter of a microelectromechanical systems (MEMS) microphone such that a combined phase and magnitude response of a cascade of the intrinsic highpass filter and the digital correcting network substantially approximates the response of a target highpass filter.

Abstract: Voltage regulators in a current share arrangement may provide a total current to a common load, and may be simultaneously turned on to ramp up member currents. Each voltage regulator may provide a respective member current in the current share configuration. A target current value may be determined from a cycle-averaged current value of the member currents and a voltage error value of the voltage regulator, and each member current may be ramped to the target current value instead of the cycle-averaged current value when the voltage regulators are turned on, resulting in more stable and balanced current ramping. A predictive multi-phase digital controller may therefore operate according to a target current determined based on a measured or inferred inductor current and an error voltage. Pulse-width, pulse position and pulse frequency (adding or skipping pulses) may be calculated according to the operation of the predictive multi-phase digital controller.

Abstract: Voltage regulators in a current share arrangement may provide a total current to a common load, and may be simultaneously turned on to ramp up member currents. Each voltage regulator may provide a respective member current in the current share configuration. A target current value may be determined from a cycle-averaged current value of the member currents and a voltage error value of the voltage regulator, and each member current may be ramped to the target current value instead of the cycle-averaged current value when the voltage regulators are turned on, resulting in more stable and balanced current ramping. A predictive multi-phase digital controller may therefore operate according to a target current determined based on a measured or inferred inductor current and an error voltage. Pulse-width, pulse position and pulse frequency (adding or skipping pulses) may be calculated according to the operation of the predictive multi-phase digital controller.

Abstract: Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input signal.

Abstract: Techniques for the estimation of sample-time and gain mismatch errors in a two-channel time interleaved analog to digital converter that are devoid of any multiplication operation. In a sample-time mismatch error evaluation, the signs and the absolute values from the two ADCs are used to provide an estimate of the sample-time mismatch error. In a gain error estimation algorithm, the absolute values of the outputs from the two ADCs are subtracted and accumulated. The errors can then be corrected, in a preferred embodiment, using suitable adaptive sample time and gain correction techniques.

Abstract: A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.

Abstract: Techniques for calibrating non-linearities of ADCs are described, which can be applied whether or not the non-linearities change with frequency. When the non-linearities do not change (are static), the frequency of a calibrating signal is first estimated coarsely in a calibration mode, then a fine estimate is determined using the coarse estimate. These estimates are then used to predict the sinusoidal signal using a linear predictor. A Look Up Table (LUT) containing corrections to the ADC is derived from this result. The LUT is then used in a normal operating mode to correct the output of the ADC. In a case where the characteristics of the non-linearities of the input signal are dynamic and thus change with frequency, a frequency spectrum of interest is broken into several regions. In each of these regions, a frequency is identified and used as a calibrating signal to generate the corresponding LUT.

Abstract: A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS1, of the M ADC subunits is selected to locate one or more integer multiples of a Nyquist frequency of a respective subunit ADC in one or more guard bands, and/or such that one or more integer multiples of FS1 are also located in the guard bands.

Abstract: Techniques for the estimation of sample-time and gain mismatch errors in a two-channel time interleaved analog to digital converter that are devoid of any multiplication operation. In a sample-time mismatch error evaluation, the signs and the absolute values from the two ADCs are used to provide an estimate of the sample-time mismatch error. In a gain error estimation algorithm, the absolute values of the outputs from the two ADCs are subtracted and accumulated. The errors can then be corrected, in a preferred embodiment, using suitable adaptive sample time and gain correction techniques.

Abstract: Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input signal.

Abstract: A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to estimating one or more of these errors, the ADC core output signals are filtered, with the filtering depending upon expected aliasing characteristics of the input signal.

Abstract: Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). A number, M, of clock signals drive a corresponding number of main ADC elements with a selected plurality of different clock phases. Each of the ADCs has at least one of an offset correction input, a gain correction input, or a phase correction input. The M digital values output by the ADCs are interleaved to form a digital representation of the input signal. Also provided is a reference ADC that outputs reference digital values in response to at least one of the M clock signals at a time. The output of the reference ADC is compared and/or combined with the output from a selected one of the main ADCs to provide an estimate of offset, gain or phase. The error is accumulated to determine a corresponding correction of offset, gain or phase which is then fed back to the respective input of the corresponding main ADC.

Abstract: Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. Calling each of the sums or averages as Xk where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, Xmean, is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from Xk?Xmean. The sign of each offset error, i.e., sign (Xk?Xmean), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC.

Abstract: Techniques for calibrating non-linearities of ADCs are described, which can be applied whether or not the non-linearities change with frequency. When the non-linearities do not change (are static), the frequency of a calibrating signal is first estimated coarsely in a calibration mode, then a fine estimate is determined using the coarse estimate. These estimates are then used to predict the sinusoidal signal using a linear predictor. A Look Up Table (LUT) containing corrections to the ADC is derived from this result. The LUT is then used in a normal operating mode to correct the output of the ADC. In a case where the characteristics of the non-linearities of the input signal are dynamic and thus change with frequency, a frequency spectrum of interest is broken into several regions. In each of these regions, a frequency is identified and used as a calibrating signal to generate the corresponding LUT.

Abstract: A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS1, of the M ADC subunits is selected to locate one or more integer multiples of a Nyquist frequency of a respective subunit ADC in one or more guard bands, and/or such that one or more integer multiples of FS1 are also located in the guard bands.

Abstract: Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. Calling each of the sums or averages as Xk where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, Xmean, is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from Xk?Xmean. The sign of each offset error, i.e., sign (Xk?Xmean), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC.

Abstract: A two-channel time-interleaved analog-to-digital converter (TIADC) system that provides for estimation and correction of offset, gain, and sample-time errors. Error in the offsets of the two ADCs that form the TIADC produces a spurious signal at the Nyquist frequency that can be used to minimize the difference of offsets of the ADCs. The difference in gain between the two ADCs produces spurious signals reflected around the Nyquist frequency whose magnitudes can be reduced by minimizing the difference in signal power between the two ADCs. An Automatic Gain Control loop corrects the scaling of the input signal due to the average of the gains of the ADCs. Phase error produces spurious signals reflected around the Nyquist frequency that are ?/2 out of phase with those due to the gain error. Minimizing the difference between the correlation of consecutive signals from the ADCs reduces the magnitude of these image tones.