Patents by Inventor Sunderarjan Mohan

Sunderarjan Mohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080072215
    Abstract: A method and apparatus for parsing signomial and geometric programs, referred to herein as “the Parser”. Signomial and Geometric programming is a unique class of mathematical problems that is useful in the study of optimization problems. The Parser is a program designed to recognize and parse both signomial and geometric programs such that they may be accepted and solved by signomial and geometric program solvers. The Parser accepts an optimization problem from a user in the form of algebraic expressions. The Parser can then identify the problem as a signomial program and can further determine if it reduces to a geometric program. If either a signomial or geometric program exists, the Parser converts the algebraic expressions to a compact numeric format that can be accepted by a computer-aided solver. In the case of a geometric program, the solver may find a global solution to the optimization problem. However, in the case of signomial program, the solver may only find a local solution.
    Type: Application
    Filed: November 19, 2007
    Publication date: March 20, 2008
    Inventors: Stephen Boyd, Xiling Shen, Mar Hershenson, Lieven Vandenberghe, Cesar Crusius, Dave Colleran, Sunderarjan Mohan
  • Patent number: 7299459
    Abstract: A method and apparatus for parsing signomial and geometric programs, referred to herein as “the Parser”. Signomial and Geometric programming is a unique class of mathematical problems that is useful in the study of optimization problems. The Parser is a program designed to recognize and parse both signomial and geometric programs such that they may be accepted and solved by signomial and geometric program solvers. The Parser accepts an optimization problem from a user in the form of algebraic expressions. The Parser can then identify the problem as a signomial program and can further determine if it reduces to a geometric program. If either a signomial or geometric program exists, the Parser converts the algebraic expressions to a compact numeric format that can be accepted by a computer-aided solver. In the case of a geometric program, the solver may find a global solution to the optimization problem. However, in the case of signomial program, the solver may only find a local solution.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: November 20, 2007
    Assignee: Sabio Labs, Inc.
    Inventors: Stephen Boyd, Xiling Shen, Mar Hershenson, Lieven Vandenberghe, Cesar Crusius, Dave Colleran, Sunderarjan Mohan
  • Patent number: 6802050
    Abstract: A method is described that involves automatically laying out a circuit structure in software by describing in a software environment the placement of a gate structure relative to a diffusion region. The gate structure has: 1) a pair of gate fingers that project over the diffusion region along a y axis; and, 2) a landing area for receiving multiple contacts from a metal 1 layer. The method also involves running a pair of source fingers at a metal 1 layer over the diffusion area and along the y axis. The pair of source fingers are outside the pair of gate fingers and are an extension of a metal 1 source wire running along an x axis. The method also involves placing a metal 1 gate pad layer over the landing area.
    Type: Grant
    Filed: April 7, 2002
    Date of Patent: October 5, 2004
    Assignee: Barcelona Design, Inc.
    Inventors: Xiling Shen, Sunderarjan Mohan
  • Patent number: 6789246
    Abstract: A method is described that involves retrieving a generic layout description of a circuit structure from a first database that stores a plurality of generic layout descriptions. The method also involves retrieving a foundry design rule profile of a semiconductor manufacturing process from a second database that stores a plurality of semiconductor manufacturing process design rule profiles.
    Type: Grant
    Filed: April 7, 2002
    Date of Patent: September 7, 2004
    Assignee: Barcelona Design, Inc.
    Inventors: Sunderarjan Mohan, Xiling Shen
  • Publication number: 20030237069
    Abstract: A method is described that involves automatically laying out a circuit structure in software by describing in a software environment the placement of a gate structure relative to a diffusion region. The gate structure has: 1) a pair of gate fingers that project over the diffusion region along a y axis; and, 2) a landing area for receiving multiple contacts from a metal 1 layer. The method also involves running a pair of source fingers at a metal 1 layer over the diffusion area and along the y axis. The pair of source fingers are outside the pair of gate fingers and are an extension of a metal 1 source wire running along an x axis. The method also involves placing a metal 1 gate pad layer over the landing area.
    Type: Application
    Filed: April 7, 2002
    Publication date: December 25, 2003
    Inventors: Sunderarjan Mohan, Xiling Shen