Abstract: A semiconductor design optimization system that includes: a data base configured to store design data, a training data preprocessing unit configured to preprocess the design data and generate training data, a data learning unit configured to generate a physical property prediction model by training using the training data, a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated, and a layout generator configured generate a design layout optimized to distribute the predicted physical property values for each region of the semiconductor device to be fabricated by modifying the design drawings based on the predicted physical

Abstract: A method of manufacturing a semiconductor device including various contact studs is provided. According to the method, a plurality of contact holes for various metal contact studs aligned to a bit line, a gate, a semiconductor substrate, or an electrode are formed simultaneously after a capacitor formation process. In this case, an etch stop pattern provided for stopping a selective etching process for forming the contact holes covers the bit line or conductive plugs formed on the semiconductor substrate. The thickness of a first etch stop pattern formed on the bit line or an electrode is similar or substantially the same as a second etch stop pattern formed on conductive plugs. To this end, the method involves selectively removing a capping insulating layer on the bit line for a self aligned contact (SAC) process for forming a conductive pad connected to a capacitor and then depositing a separate etch stop layer.