Abstract: Disclosed is a system for predicting the lifetime of a battery being chargeable and dischargeable using charge-discharge characteristics in a Battery Management System (BMS). The system includes: a battery state measurement unit measuring a voltage, a State of Charge (SOC), and a Depth of Discharge (DOD) of a battery while charging and discharging the battery with changing charge current and discharge current; an irreversible energy amount deriving unit deriving an irreversible energy amount (Qir) that is generated when the battery is charged/discharged from the voltage and the SOC using enthalpy and entropy theory; and a remaining lifetime prediction unit predicting a remaining lifetime of the battery from the derived irreversible energy amount (Qir), in which the remaining lifetime of the battery is predicted by equation ? k = 1 n Q ir_k min ? ( mQ ir_m · ? k = 1 n Q ir_k ) = N a N p .

Abstract: Provided is a system of designing a seismic isolation mount for protecting electrical equipment comprising switchboard and control panel from earthquakes.

Abstract: Disclosed is a system for predicting the lifetime of a battery being chargeable and dischargeable using charge-discharge characteristics in a Battery Management System (BMS). The system includes: a battery state measurement unit measuring a voltage, a State of Charge (SOC), and a Depth of Discharge (DOD) of a battery while charging and discharging the battery with changing charge current and discharge current; an irreversible energy amount deriving unit deriving an irreversible energy amount (Qir) that is generated when the battery is charged/discharged from the voltage and the SOC using enthalpy and entropy theory; and a remaining lifetime prediction unit predicting a remaining lifetime of the battery from the derived irreversible energy amount (Qir), in which the remaining lifetime of the battery is predicted by equation ? k = 1 n ? Q ir_k min ? ? ( mQ ir_m · ? k = 1 n ? Q ir_k ) = N a N p .

Abstract: The present invention discloses a method of manufacturing a dual chip package using tape wiring boards. According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are prepared. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad.

Abstract: The present invention discloses a method of manufacturing a dual chip package using tape wiring boards. According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are prepared. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad.

Abstract: The present invention discloses a method of manufacturing a dual chip package using tape wiring boards. According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are prepared. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad.

Abstract: The present invention discloses a method of manufacturing a dual chip package using tape wiring boards. According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are prepared. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad.