Patents by Inventor Sung-Gil Choi
Sung-Gil Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240081001Abstract: A display device includes a display panel having a folding axis extending in a first direction; and a panel supporter disposed on a surface of the display panel. The panel supporter includes a first layer including a first base resin and first fiber yarns extending in the first direction and dispersed in the first base resin, a second layer disposed on the first layer, the second layer including a second base resin and second fiber yarns extending in a second direction intersecting the first direction and dispersed in the second base resin, and a third layer disposed on the second layer, the third layer including a third base resin and third fiber yarns extending in the first direction and dispersed in the third base resin.Type: ApplicationFiled: May 1, 2023Publication date: March 7, 2024Applicant: Samsung Display Co., LTD.Inventors: Soh Ra HAN, Yong Hyuck LEE, Hong Kwan LEE, Hyun Jun CHO, Min Ji KIM, Sung Woo EO, Eun Gil CHOI, Sang Woo HAN
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Patent number: 8704283Abstract: A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.Type: GrantFiled: March 16, 2010Date of Patent: April 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Kyu Kim, Sang-Sup Jeong, Sung-Gil Choi, Heung-Sik Park, Kuk-Han Yoon, Yong-Joon Choi
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Patent number: 8053358Abstract: Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material.Type: GrantFiled: December 10, 2010Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-young Lee, Sang-sup Jeong, Sung-gil Choi, Jong-chul Park, Jin-young Kim, Ki-jin Park
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Patent number: 7875551Abstract: Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material.Type: GrantFiled: October 8, 2009Date of Patent: January 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-young Lee, Sang-sup Jeong, Sung-gil Choi, Jong-chul Park, Jin-young Kim, Ki-jin Park
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Publication number: 20100237466Abstract: A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.Type: ApplicationFiled: March 16, 2010Publication date: September 23, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Kyu Kim, Sang-Sup Jeong, Sung-Gil Choi, Heung-Sik Park, Kuk-Han Yoon, Yong-Joon Choi
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Publication number: 20100112803Abstract: Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material.Type: ApplicationFiled: October 8, 2009Publication date: May 6, 2010Inventors: Doo-young Lee, Sang-sup Jeong, Sung-gil Choi, Jong-chul Park, Jin-young Kim, Ki-jin Park
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Publication number: 20090184391Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.Type: ApplicationFiled: March 10, 2009Publication date: July 23, 2009Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
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Patent number: 7557026Abstract: In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.Type: GrantFiled: February 27, 2007Date of Patent: July 7, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Kyu Kim, Sang-Sup Jeong, Sung-Gil Choi, Kuk-Han Yoon, Bum-Soo Kim
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Publication number: 20090117723Abstract: In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.Type: ApplicationFiled: October 15, 2008Publication date: May 7, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-Kyu Kim, Bum-Soo Kim, Jong-Heui Song, Sang-Sup Jeong, Sung-Gil Choi, Kuk-Han Yoon
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Patent number: 7510914Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.Type: GrantFiled: June 7, 2006Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
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Publication number: 20090014833Abstract: An exemplary semiconductor device includes a semiconductor substrate on which lower electrodes are formed. The lower electrodes are arranged in an array including a rows extending substantially parallel to one another along a first direction. A stripe-shaped capacitor support pad is interposed between a pair of adjacent ones of the rows and is connected to lower electrodes in the pair of adjacent ones of the rows. The semiconductor device may include plurality of capacitors each including a one of the lower electrodes, a dielectric film, and an upper electrode. An upper end of the capacitor support pad is below the upper ends of the lower electrodes. A portion of the stripe-shaped capacitor support pad is interposed between adjacent ones of lower electrodes included within at least one of the rows and is connected to the adjacent ones of lower electrodes included within the at least one of the rows.Type: ApplicationFiled: July 10, 2008Publication date: January 15, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kuk-Han YOON, Jong-Kyu KIM, Sang-Sup JEONG, Sung-Gil CHOI, Tae-Hyuk AHN
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Publication number: 20080096378Abstract: In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.Type: ApplicationFiled: February 27, 2007Publication date: April 24, 2008Inventors: Jong-Kyu Kim, Sang-Sup Jeong, Sung-Gil Choi, Kuk-Han Yoon, Bum-Soo Kim
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Publication number: 20070184694Abstract: Example embodiments relate to a wiring structure, a semiconductor device and methods of forming the wiring structure. The wiring structure may include a first contact plug, a second contact plug, a protecting layer pattern and an insulating structure. The first contact plug may be provided on a semiconductor substrate. The second contact plug may be provided on the first contact plug to be electrically connected to the first contact plug. The protecting layer pattern may encompass an upper sidewall of the first contact plug and a sidewall of the second contact plug to retard chemicals from infiltrating into an interface between the first and second contact plugs. The insulating structure may encompass the first contact plug, the second contact plug and the protecting layer pattern.Type: ApplicationFiled: November 3, 2006Publication date: August 9, 2007Inventors: Jong-Kyu Kim, Jong-Chul Park, Jang-Bin Yim, Sang-Dong Kwon, Ki-Jeong Kim, Sung-Gil Choi
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Publication number: 20070066056Abstract: Example embodiments of the present invention provide a method of removing a photoresist and a method of manufacturing a semiconductor device using the same. In a method of removing a photoresist and a method of manufacturing a semiconductor device, a plasma including active ions and radicals may be generated. The active ions may be modified into directional active ions. The photoresist may be etched using the directional active ions as main etching factors and/or the radicals as subsidiary etching factors. The photoresist may be completely removed from the semiconductor device such as a lower electrode. Thus, the likelihood of an increase in electrical resistance due to residual photoresist may decrease.Type: ApplicationFiled: June 6, 2006Publication date: March 22, 2007Inventors: Jong-Kyu Kim, Sung-Gil Choi, Jang-Bin Yim, Sang-Dong Kwon, Ki-Jeong Kim
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Patent number: 7161205Abstract: There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.Type: GrantFiled: November 18, 2004Date of Patent: January 9, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Gil Choi, Sang-Sup Jeong
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Publication number: 20060289899Abstract: Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.Type: ApplicationFiled: June 7, 2006Publication date: December 28, 2006Inventors: Hyun-Chul Yoon, Jong-Kyu Kim, Jang-Bin Yim, Sang-Dong Kwon, Sung-Gil Choi
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Publication number: 20060046382Abstract: In an embodiment, a method of forming a capacitor for a semiconductor device of which structural stability is improved is shown. Cylindrical storage electrodes are formed in a matrix pattern on a substrate that includes an insulation interlayer having contacts therein so that a mold layer surrounds the cylindrical storage electrodes. Sacrificial plugs are formed with a cap within these electrodes. A stabilizing layer is formed on the etched mold layer and the cylindrical storage electrode by partially etching the mold layer. The stabilizing layer is etched until the sacrificial plug is exposed, thereby forming a spacer. While the sacrificial plug and the mold layer are fully removed, the spacer is partially removed, thereby forming a stabilizing member for supporting neighboring storage electrodes adjacent to each other. Accordingly, a structural stability of the capacitor is improved.Type: ApplicationFiled: August 17, 2005Publication date: March 2, 2006Inventors: Kuk-Han Yoon, Sang-Sup Jeong, Sung-Gil Choi, Jong-Kyu Kim
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Publication number: 20050167724Abstract: There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.Type: ApplicationFiled: November 18, 2004Publication date: August 4, 2005Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Gil Choi, Sang-Sup Jeong
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Patent number: 6653228Abstract: A method for forming a contact hole in a semiconductor device includes the steps of forming a polymer layer on an upper portion and a side wall of photo resist mask, while etching an oxide layer under the photoresist mask to form a contact hole that uses an etchant gas comprising CH2F2 gas; and etching the oxide layer while stopping the supply of CH2F2 gas to the etching process.Type: GrantFiled: November 29, 2001Date of Patent: November 25, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Gil Choi, Tae-Hyuk Ahn
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Patent number: 6451663Abstract: A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.Type: GrantFiled: October 24, 2001Date of Patent: September 17, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Gil Choi, Tae Hyuk Ahn, Sang Sup Jeong, Dae Hyuk Chung, Won Jun Lee