Patents by Inventor Sung-gon Jung
Sung-gon Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8930859Abstract: Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.Type: GrantFiled: July 17, 2013Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Sung-Gon Jung
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Patent number: 8913071Abstract: An image signal modifying device includes a pixel, a memory which stores compressed information in which a three-dimensional (ā3-Dā) lookup table is coded, an image signal modifying unit which decodes the compressed information to generate a restored 3-D lookup table and generates a modified signal based on a first image signal of a first frame, a second image signal of a second frame, a third image signal of a third frame and the restored 3-D lookup table, and a data driver which converts the modified signal into the data voltage and supplies the data voltage to the pixel.Type: GrantFiled: August 23, 2011Date of Patent: December 16, 2014Assignee: Samsung Display Co., Ltd.Inventors: Sung Gon Jung, Sang Su Han, Seok Hwan Roh
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Publication number: 20140231925Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: ApplicationFiled: April 29, 2014Publication date: August 21, 2014Inventors: Man-Hyoung RYOO, Gi-Sung YEO, Si-Hyeung LEE, Gyu-Chul KIM, Sung-Gon JUNG, Chang-Min PARK, Hoo-Sung CHO
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Publication number: 20140033152Abstract: Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.Type: ApplicationFiled: July 17, 2013Publication date: January 30, 2014Inventor: Sung-Gon JUNG
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Patent number: 8338310Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask andType: GrantFiled: May 25, 2010Date of Patent: December 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-gon Jung, Suk-joo Lee, Woo-sung Han, Seong-woon Choi
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Publication number: 20120256904Abstract: An image signal modifying device includes a pixel, a memory which stores compressed information in which a three-dimensional (ā3-Dā) lookup table is coded, an image signal modifying unit which decodes the compressed information to generate a restored 3-D lookup table and generates a modified signal based on a first image signal of a first frame, a second image signal of a second frame, a third image signal of a third frame and the restored 3-D lookup table, and a data driver which converts the modified signal into the data voltage and supplies the data voltage to the pixel.Type: ApplicationFiled: August 23, 2011Publication date: October 11, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Gon JUNG, Sang Su HAN, Seok Hwan ROH
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Publication number: 20120206429Abstract: A method of processing data including dividing, at a transmitter, data into 3-bit units, generating, at the transmitter, first and second clock embedded data signals and a third data signal, wherein a clock signal and first bits of the units are included in the first clock embedded data signal, the clock signal and second bits of the units are included in the second clock embedded data signal and third bits of the units are included in the third data signal, transmitting, from the transmitter to a receiver, the first and second clock embedded data signals and the third data signal, and restoring, at the receiver, the first and second bits and the clock signal from the first and second clock embedded data signals and the third bits from the third data signal.Type: ApplicationFiled: December 6, 2011Publication date: August 16, 2012Inventors: Sang-Keun Lee, Seung-Seok NAM, Sung-Gon JUNG, Sang-Su HAN
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Patent number: 8193047Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: GrantFiled: January 4, 2010Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Man-Hyoung Ryoo, Gi-Sung Yeo, Si-Hyeung Lee, Gyu-Chul Kim, Sung-Gon Jung, Chang-Min Park, Hoo-Sung Cho
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Publication number: 20110156159Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Inventors: Man-Hyoung Ryoo, Gi-Sung Yeo, Si-Hyeung Lee, Gyu-Chul Kim, Sung-Gon Jung, Chang-Min Park, Hoo-Sung Cho
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Patent number: 7892982Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.Type: GrantFiled: October 30, 2007Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-youl Lee, Pan-suk Kwak, Sung-gon Jung, Jung-hyeon Lee, Suk-joo Lee, Cha-won Koh, Ji-young Lee
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Patent number: 7873935Abstract: A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based Self-Aligning Double Patterning (SADP) emulation, comparing the first emulation pattern with the first mask data pattern, and modifying the second mask data pattern according to results of the comparison. The method further includes performing Optical Proximity Correction (OPC) on the modified second mask data pattern, acquiring second emulation patterns, which are predicted from the second mask data pattern on which the OPC has been performed, using image-based SADP emulation, and comparing the second emulation patterns and the first mask data pattern and manufacturing a first mask layer, which corresponds to the second mask data pattern on which the OPC has been performed, according to the results of the comparison.Type: GrantFiled: June 14, 2007Date of Patent: January 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-gon Jung, Ji-young Lee, Han-ku Cho, Gi-sung Yeo
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Publication number: 20100297852Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask andType: ApplicationFiled: May 25, 2010Publication date: November 25, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-gon Jung, Suk-joo Lee, Woo-sung Han, Seong-woon Choi
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Publication number: 20100190303Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: ApplicationFiled: January 4, 2010Publication date: July 29, 2010Inventors: Man-Hyoung Ryoo, Gi-Sung Yeo, Si-Hyeung Lee, Gyu-Chul Kim, Sung-Gon Jung, Chang-Min Park, Hoo-Sung Cho
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Patent number: 7687369Abstract: A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.Type: GrantFiled: September 4, 2007Date of Patent: March 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Jeong-lim Nam, Gi-sung Yeo, Sang-jin Kim, Sung-gon Jung
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Patent number: 7604907Abstract: Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.Type: GrantFiled: October 4, 2005Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Youl Lee, Seok-Hwan Oh, Gi-Sung Yeo, Sang-Gyun Woo, Sook Lee, Joo-On Park, Sung-Gon Jung
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Patent number: 7539970Abstract: A method of manufacturing a mask includes designing a second mask data pattern for forming a first mask data pattern, creating a first emulation pattern, which is determined from the second mask data pattern, using a first emulation, creating a second emulation pattern, which is determined from the first emulation pattern, using a second emulation, comparing a pattern, in which the first and second emulation patterns overlap, with the first mask data pattern, and manufacturing a mask layer, which corresponds to the second mask data pattern, according to results of the comparison.Type: GrantFiled: October 31, 2006Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Gon Jung, Gi-Sung Yeo, Young-Mi Lee, Han-Ku Cho
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Patent number: 7473497Abstract: A phase shifting mask (PSM) for manufacturing a semiconductor device and a method of fabricating the same includes a transparent substrate, a main pattern formed on the transparent substrate and comprising a first phase shifting layer having a first optical transmittance greater than 0, and at least one assistant pattern formed on the transparent substrate proximal to the main pattern for phase-shifting by the same degree as the main pattern and having a second optical transmittance, which is less than the first optical transmittance.Type: GrantFiled: March 18, 2005Date of Patent: January 6, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: In-sung Kim, Jung-hyeon Lee, Sung-gon Jung
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Patent number: 7452825Abstract: In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.Type: GrantFiled: October 30, 2006Date of Patent: November 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Youl Lee, Han-Ku Cho, Suk-Joo Lee, Gi-Sung Yeo, Cha-Won Koh, Sung-Gon Jung
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Publication number: 20080200026Abstract: A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.Type: ApplicationFiled: September 4, 2007Publication date: August 21, 2008Inventors: Cha-won Koh, Jeong-lim Nam, Gi-sung Yeo, Sang-jin Kim, Sung-gon Jung
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Publication number: 20080124931Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.Type: ApplicationFiled: October 30, 2007Publication date: May 29, 2008Inventors: Doo-youl Lee, Pan-suk Kwak, Sung-gon Jung, Jung-hyeon Lee, Suk-joo Lee, Cha-won Koh, Ji-young Lee