Patents by Inventor Sung Hoon Chung

Sung Hoon Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050266648
    Abstract: Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein that extend opposite the active region. A trench mask having a second plurality of openings therein is then formed by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask. A plurality of trenches are then formed in the active region by etching the semiconductor substrate using the trench mask as an etching mask. A plurality of insulated gate electrodes are then formed that extend into the plurality of trenches.
    Type: Application
    Filed: April 19, 2005
    Publication date: December 1, 2005
    Inventors: Sung-hoon Chung, Byeong-yun Nam, Kyeong-koo Chi
  • Publication number: 20050001252
    Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
    Type: Application
    Filed: June 2, 2004
    Publication date: January 6, 2005
    Inventors: Yong-Jin Kim, Kyeong-Koo Chi, Chang-Jin Kang, Hyoung-Sub Kim, Myeong-Cheol Kim, Tae-Rin Chung, Sung-Hoon Chung, Ji-Young Kim