Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

Abstract: The present technology includes a data strobe clock output circuit. The data strobe clock output circuit includes a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal and output a first data strobe clock in response to the rising clock, the falling clock, and mode signals, and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signals.

Abstract: A semiconductor memory device operated under control of a controller. The semiconductor memory device including a control logic and a data input/output circuit. The control logic configured to store logic data and generate a plurality of pieces of circular data based on the logic data in response to an output command of the logic data that is received from the controller. The data input/output circuit configured to select circular data corresponding to a set warm-up cycle among the plurality of pieces of circular data and output the selected circular data to the controller.

Abstract: The present technology includes a data strobe dock output circuit. The data strobe clock output circuit includes a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal and output a first data strobe clock in response to the rising clock, the falling clock, and mode signals, and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signals.

Abstract: A semiconductor memory device operated under control of a controller. The semiconductor memory device including a control logic and a data input/output circuit. The control logic configured to store logic data and generate a plurality of pieces of circular data based on the logic data in response to an output command of the logic data that is received from the controller. The data input/output circuit configured to select circular data corresponding to a set warm-up cycle among the plurality of pieces of circular data and output the selected circular data to the controller.

Abstract: The present technology relates to a memory device that generates various signals used in a read training operation and a method of operating the memory device. The memory device according to an embodiment of the present disclosure includes an address counter configured to generate a plurality of count signals based on a read training enable signal and a first clock signal received from a memory controller, and an address section identification signal generator configured to generate address section identification signals used in identifying a plurality of address sections based on at least one of the plurality of count signals.

Abstract: The present technology relates to a memory device that generates various signals used in a read training operation and a method of operating the memory device. The memory device according to an embodiment of the present disclosure includes an address counter configured to generate a plurality of count signals based on a read training enable signal and a first clock signal received from a memory controller, and an address section identification signal generator configured to generate address section identification signals used in identifying a plurality of address sections based on at least one of the plurality of count signals.

Abstract: Various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device including a plurality of memory cells using an optimal input buffer reference voltage may include at least one input buffer receiving data to be stored in the plurality of memory cells, and an input buffer reference voltage control unit setting one of a plurality of internal voltages generated beforehand and having different voltage levels as a reference voltage of the at least one input buffer in response to a control signal received from a controller controlling the semiconductor memory device.

Abstract: Various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device including a plurality of memory cells using an optimal input buffer reference voltage may include at least one input buffer receiving data to be stored in the plurality of memory cells and an input buffer reference voltage control unit setting one of a plurality of internal voltages having different voltage levels as a reference voltage of the at least one input buffer in response to a control signal.

Abstract: A semiconductor device includes a pipeline latch unit including a plurality of write pipelines, and suitable for latching data, and a control unit suitable for controlling at least one write pipeline of the write pipelines based on an idle signal.

Abstract: A semiconductor device includes a mode register set suitable for generating a first internal control signal and a second internal control signal, a per-DRAM addressability (PDA) driving unit suitable for resetting the mode register set in response to the first internal control signal and an input value of data inputted through a data pad, and a cycle redundancy check (CRC) driving unit suitable for performing a CRC operation by checking whether or not data are correctly inputted through the data pad without an error in response to the first internal control signal and the second internal control signal.

Abstract: A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode.

Abstract: A semiconductor device includes an error detection unit suitable for receiving data and a cyclic redundancy check (CRC) code, and for outputting a detection signal by detecting a transmission error of the data, and a signal change unit suitable for generating error information based on the detection signal while changing a signal form of the error information based on a signal transmission environment of the data.

Abstract: A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.

Abstract: A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode.

Abstract: A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.

Abstract: A semiconductor device includes a pipeline latch unit including a plurality of write pipelines, and suitable for latching data, and a control unit suitable for controlling at least one write pipeline of the write pipelines based on an idle signal.

Abstract: A semiconductor device includes an error detection unit suitable for receiving data and a cyclic redundancy check (CRC) code, and for outputting a detection signal by detecting a transmission error of the data, and a signal change unit suitable for generating error information based on the detection signal while changing a signal form of the error information based on a signal transmission environment of the data.

Abstract: A semiconductor device includes a mode register set suitable for generating a first internal control signal and a second internal control signal, a per-DRAM addressability (PDA) driving unit suitable for resetting the mode register set in response to the first internal control signal and an input value of data inputted through a data pad, and a cycle redundancy check (CRC) driving unit suitable for performing a CRC operation by checking whether or not data are correctly inputted through the data pad without an error in response to the first internal control signal and the second internal control signal.