Abstract: A deposition mask includes a mask main body and a coating layer. The mask main body includes a plurality of slits penetrating the mask main body. The coating layer is coated on an entire surface of the mask main body. The coating layer is made of a material different from a material of the main body, and it has a magnetic force stronger than that of the main body. Each of the slits has an open area, and a thickness of the coating layer controls a width of the open area. A photolithography process is used to form the plurality of slits.

Abstract: A method of fabricating a semiconductor device and a flash memory device are provided. The method of fabricating the semiconductor device includes: forming a nitride film on a semiconductor substrate; forming a sacrificial vertical structure on the nitride film; forming sacrificial spacers on lateral surfaces of the sacrificial vertical structure; performing an initial patterning of the nitride film using the sacrificial vertical structure and the sacrificial spacers as etch masks; removing the sacrificial spacers after the initial patterning of the nitride film and forming gate electrodes on the lateral surfaces of the sacrificial vertical structure; and removing the sacrificial vertical structure from between the gate electrodes and performing a secondary patterning of the nitride film using the gate electrodes as etch masks.

Abstract: A semiconductor device includes a semiconductor substrate, a gate formed over the semiconductor substrate, a source region formed in the semiconductor substrate at one side of the gate, a drain region formed in the semiconductor substrate at another side of the gate, and a channel region formed between the source region and the drain region, the channel region including a first channel region having a first threshold voltage and a second channel region having a second threshold voltage higher than the first threshold voltage. Accordingly, the semiconductor device has two channel regions having different threshold voltages.

Abstract: A method of fabricating a semiconductor device and a flash memory device are provided. The method of fabricating the semiconductor device includes: forming a nitride film on a semiconductor substrate; forming a sacrificial vertical structure on the nitride film; forming sacrificial spacers on lateral surfaces of the sacrificial vertical structure; performing an initial patterning of the nitride film using the sacrificial vertical structure and the sacrificial spacers as etch masks; removing the sacrificial spacers after the initial patterning of the nitride film and forming gate electrodes on the lateral surfaces of the sacrificial vertical structure; and removing the sacrificial vertical structure from between the gate electrodes and performing a secondary patterning of the nitride film using the gate electrodes as etch masks.

Abstract: A semiconductor device and a method of fabricating a semiconductor device is provided. The semiconductor device can include a semiconductor substrate; an interlayer dielectric layer having a damascene pattern formed on the semiconductor substrate; a diffusion barrier formed in the damascene pattern and made of a trivalent material; a seed layer formed on the diffusion barrier; and a copper interconnection formed on the seed layer. In one embodiment, the trivalent material is CoFeB.

Abstract: An NOR flash memory device having a back end of line (BEOL) structure, the BEOL structure including a substrate having a conductive region, a first intermetal dielectric layer formed on the substrate, a first metal line formed on the conductive region, a second intermetal dielectric layer formed on the first metal line and the first inter metal dielectric, a first contact extending through the second intermetal dielectric layer, and a second metal line connected to the first metal line through the first contact. At least one of the first contact and the first and second metal lines is composed of copper and at least one of the first and second intermetal dielectric layers is composed of a low diectrice material. The use of copper metal lines and intermetal dielectric layers composed of a low-k (k=3.0) material makes it possible to improve 40% or more in the time constant delay.

Abstract: A method of manufacturing a flash memory that can include forming a titanium nitride (TiN) layer on the pre-metal dielectric having the via hole and then forming a TiSiN layer by injecting silane (SiH4) gas on a semiconductor substrate having the titanium nitride layer; and then forming a contact by filling the via hole having the TiSiN layer.

Abstract: Provided is a method for forming a metal line of a semiconductor device. A trench is formed in an interlayer insulating layer formed on a semiconductor substrate. Copper is deposited in the trench to form a copper metal line, and a diffusion barrier layer is formed on the interlayer insulating layer and the copper metal line. A metal pad is formed on the diffusion barrier layer. In one embodiment, the diffusion barrier layer is formed of three layers, including TiSiN layers.

Abstract: A semiconductor device and a manufacturing method thereof are provided. A gate electrode and source/drain areas are disposed on a semiconductor substrate, and an interlayer dielectric layer is on the gate electrode, the source/drain areas, and the semiconductor substrate. Metal silicide layers are disposed in the gate electrode and the source/drain areas at regions exposed by contact holes.

Abstract: Disclosed is a method of forming an interconnection of a semiconductor device. The method includes forming a lower interlayer insulating layer including a lower metal interconnection on a semiconductor substrate, forming an insulating layer and an upper interlayer insulating layer on the lower interlayer insulating layer, forming a damascene pattern of a contact hole or of a trench and a contact hole in the upper interlayer insulating layer, removing the insulating layer on the lower metal interconnection and in the same chamber forming a barrier metal layer on the damascene pattern having no insulating layer, removing the barrier metal layer on the lower metal interconnection, filling the damascene pattern with metal, and forming a metal interconnection by polishing the damascene pattern.

Abstract: Embodiments relate to a method of manufacturing a semiconductor device, which may facilitate high integration of the device and may prevent undercut form occurring. In embodiments, the method may include forming a gate insulating film on a semiconductor substrate, forming, on the gate insulating film, a gate electrode having a spacer formed on both sidewalls thereof, forming a source/drain region in regions of the substrate located at both sides of the gate electrode, forming a non-salicide film on the entire surface of the substrate, performing a wet process and a pre-cleaning process with respect to a region of the non-salicide film in which a salicide film will be formed, forming the salicide film on the gate electrode and the source/drain region, and performing a primary annealing process, a wet etching process, a secondary annealing process with respect to the salicide film.

Abstract: A manufacturing method of a semiconductor device including at least one of the following steps. Forming a gate insulating layer, a gate electrode layer, a spacer, a source region and a drain region on and/or over a substrate on which a predetermined lower structure is formed. Making the upper portion of the gate electrode layer and the upper portions of the source and the drain an amorphous structure using a pre-amorphization implant process. Removing the native oxide on the upper portion of the gate electrode layer and the upper portions of the source and the drain by performing a pre-cleaning process. Forming an oxide film on the upper portion of the gate electrode layer and the upper portions of the source and the drain.

Abstract: A method for monitoring a deposition temperature of a Cu seed layer by measuring an optical reflectivity of the Cu seed layer deposited on a substrate; and estimating the deposition temperature of the Cu seed layer by comparing the measured optical reflectivity with a reference optical reflectivity of a reference Cu seed layer in which an agglomeration phenomenon has not happened. The estimating step includes computing the deposition temperature of the Cu seed layer at a temperature higher than about ?25° C. which is a reference deposition temperature for depositing the reference Cu seed layer if the measured reflectivity is smaller than the reference optical reflectivity.