Abstract: A display substrate includes a data line, a gate line and a fan-out line. The data line is disposed in a display area of a base substrate and transfers a data signal to a switching element electrically connected to a pixel electrode. The gate line is disposed in the display area and transfers a gate signal to the switching element. The fan-out line is disposed in a peripheral area of the base substrate surrounding the display area, electrically connected to at least one of the data line and the gate line, and includes a plurality of conductive layers making contact with each other through a contact hole.

Abstract: A liquid crystal display includes pixels which is disposed in row and column directions, respectively includes pixel electrodes, and arranged along a first pixel column to a sixth pixel column, gate lines including pairs of two adjacent gate lines for each pixel row in the row direction, data lines including a first data line at a left side of the first pixel column, a second data line between the second and third pixel columns, a third data line between the fourth and fifth pixel columns, and a fourth data line at a right side of the sixth pixel column; and common voltage lines including a first common voltage line between the first and second pixel columns, a second common voltage line between the third and fourth pixel columns, and a third common voltage line between the fifth and sixth pixel columns.

Abstract: A thin film transistor array panel includes a first insulation substrate, a gate line and a data line which are positioned on the first insulation substrate, are insulated from each other, and cross each other, a thin film transistor connected to the gate line and the data line, an organic film positioned on the thin film transistor, a second passivation layer which is positioned on the organic film and defines a plurality of second openings therein, a common electrode positioned on the second passivation layer, and a pixel electrode positioned in the plurality of second openings, where a thickness of the common electrode is larger than a thickness of the pixel electrode.

Abstract: A display device may include an insulating layer. The display device may further include a first field-generating electrode that overlaps the insulating layer. The display device may further include a second field-generating electrode that overlaps the first field-generating electrode and has a cutout. An exposed portion of the insulating layer may be exposed through the cutout and may be exposed between an edge (or boundary) of the first field-generating electrode and an end portion of the second field-generating electrode in a layout view of the display device.

Abstract: Exemplary embodiments of the present disclosure provide a thin film transistor array panel including a first insulating substrate; a gate line and a data line disposed on the first insulating substrate, intersecting with each other, and being insulated from each other; a first passivation layer disposed on the gate line and the data line and comprising a plurality of first openings; a first electrode disposed on the first passivation layer; and a second electrode disposed in the first opening, thereby simplifying a manufacturing process of the thin film transistor array panel.

Abstract: A display panel includes a gate driver connected to a gate line, where the gate driver includes a plurality of stages, where each of the stages includes at least one dual gate thin film transistor having a first control terminal and a second control terminal, and where each of the stages receives a clock signal, a first low voltage, a second low voltage, at least one transmission signal of previous stages, at least two transmission signals of subsequent stages and an output control signal from one of the stages to output a gate voltage including a gate-on voltage and a gate-off voltage.

Abstract: This invention relates to an aluminum pouch film for a secondary battery, including an aluminum layer; an outer layer formed on the first surface of the aluminum layer; a first adhesive layer for adhering the aluminum layer and the outer layer; an inner layer formed on the second surface of the aluminum layer and configured to include a crosslinked polymer layer; and a second adhesive layer for adhering the aluminum layer and the inner layer.

Abstract: A method for manufacturing a touch sensor panel with a reduced number of masks includes forming a first resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of first sensor electrodes; etching a first transparent conductive layer and a first other conductive layer using the first resist layer patterns having both full and partial thicknesses; forming a second resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of second sensor electrodes; and etching while using the second resist layer patterns.

Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

Abstract: A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having an output terminal electrically connected to a respective one of the plurality of gate lines. The multiple signal applying unit applies a sub scan signal and a main scan signal. The sub scan signal and the main scan signal sequentially activate each of the plurality of gate lines. Therefore, the scan lines receive the scan signal twice, so that the liquid crystal capacitors electrically connected to the gate lines receive the data voltage twice. As a result, even though the time for charging the liquid crystal capacitors may be reduced, the liquid crystal capacitors may be fully charged to enhance display quality.

Abstract: A liquid crystal display includes a first substrate, gate lines and data lines disposed on a display area of the first substrate, a common voltage line disposed on a peripheral area of the first substrate, a common voltage transmission unit extending from the common voltage line, an organic layer disposed on the common voltage transmission unit and the common voltage line, a connecting member disposed on the organic layer disposed on the peripheral area, a first insulating layer disposed on the pixel electrode and the connecting member, a common electrode disposed on the first insulating layer, and a short point connecting the connecting member and the common electrode to each other. The common electrode and the first insulating layer include a plurality of cutouts in the peripheral region and display region of the first substrate which have substantially a same plane shape as each other.

Abstract: A liquid crystal display includes a plurality of pixel electrodes and common electrodes disposed on a first substrate that overlap each other with a passivation layer interposed therebetween, and a connection portion disposed between a common voltage applying unit and the common electrode. The common electrode has a plurality of first cutouts, the passivation layer has a plurality of second cutouts, and the first cutout and the second cutout have substantially the same planar shape. The connection portion includes a lower connection portion formed from a same layer as the common electrode, and an upper connection portion disposed on the lower connection portion that includes a low resistance metal.

Abstract: A liquid crystal display, includes: a substrate; a gate line including a gate pad and a data line including a data pad, the gate and data lines being disposed on the substrate; a thin film transistor connected to the gate line and the data line; an organic layer disposed on the thin film transistor; a pixel electrode disposed on the organic layer; a first contact assistant disposed on the gate pad; a second contact assistant disposed on the data pad; a first insulating layer disposed on the pixel electrode; and a common electrode disposed on the first insulating layer, the common electrode overlapping with the pixel electrode. The common electrode includes first cutouts, the first insulating layer includes second cutouts, the plane shapes of the first and second cutouts are substantially the same, and the pixel electrode includes a polycrystalline transparent conductive material.

Abstract: In a thin film transistor array panel and a method of manufacturing the same, a thin passivation layer is positioned between a first field generating electrode and a second field generating electrode. The thin passivation layer overlaps the first and second field generating electrodes. The thin passivation layer includes a transparent photosensitive organic material. When forming the first field generating electrode, the passivation layer is used as a photosensitive film. Accordingly, the passivation layer and the first field generating electrode may be formed using a same single photo-mask. Accordingly, the manufacturing cost of the thin film transistor array panel may be reduced.

Abstract: A display, includes: a substrate; first signal lines (FSLs) at least partially recessed in the substrate and extending in substantially a direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

Abstract: A substrate includes a storage line, first and second gate lines and first and second pixel electrodes. The storage line extends along a first direction on the substrate. The first and second gate lines are substantially parallel with the storage line. The first pixel electrode is formed between the first gate line and the storage line. The second pixel electrode is formed between the second gate line and the storage line.

Abstract: A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.

Abstract: A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.