Abstract: Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits.

Abstract: Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits.

Abstract: The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

Abstract: A circuit for controlling timing skew in a semiconductor memory device includes a skew control circuit that is configured generate separate skew control signals for each respective one of a plurality of memory banks included in the semiconductor memory device. Related methods are also disclosed.

Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in syn

Abstract: Semiconductor memory devices include a memory cell array region having a plurality of memory cells, a local data I/O line pair that is electrically connected to the plurality of memory cells, a local sense amplifier that is electrically connected to the local data I/O line pair, a read global data I/O line pair that is electrically connected to the local sense amplifier and that is configured to transmit data during a read operation and a write global data I/O line pair that is electrically connected to the local sense amplifier that is configured to transmit data during a write operation.

Abstract: A redundancy repair circuit and method therefor for use with a semiconductor memory device are provided. The redundancy repair circuit comprises: a memory circuit having a plurality of address lines and a plurality of redundancy address lines in a memory cell; a repair redundancy control circuit for repairing a defective address line using a redundancy address line of the plurality of redundancy address lines, and for encoding and outputting fuse repair information corresponding to redundancy address information, wherein addresses corresponding to defective memory cells are pre-programmed; and a redundancy line driver for receiving the fuse repair information from the repair redundancy control circuit, for decoding the fuse repair information and for activating a redundancy line corresponding to the decoded fuse repair information, wherein the repair redundancy control circuit is separate from the redundancy line driver.

Abstract: The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

Abstract: Provided are a buffer circuit and a memory system for selectively outputting a data strobe signal according to the number of data bits. The buffer circuit includes a first buffer unit, a second buffer unit, and a third buffer unit. The first buffer unit amplifies and outputs a first signal. The second buffer unit amplifies and outputs a second signal or outputs the first signal according to the logic level of a control signal. The third buffer unit amplifies the first signal to send or not to send the amplified first signal to the second buffer unit depending on the logic level of an inverted control signal. The logic levels of the control signal and the inverted control signal are determined according to the number of processed data bits.

Abstract: An integrated circuit memory device can include a memory cell array having a plurality of memory cells, and a bit line sense amplifier configured to amplify data on a pair of bit lines from a memory cell of the memory cell array and to provide the amplified data on a data line and a complementary data line. An active load circuit includes a first load device electrically connected between the data line and a voltage source wherein an electrical resistance of the first load device is varied responsive to a voltage level of the data line. The active load circuit also includes a second load device electrically connected between the complementary data line and the voltage source wherein an electrical resistance of the second load device is varied responsive to a voltage level of the complementary data line. Related methods are also discussed.

Abstract: Delay line circuits and methods include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding unit delay cell is connected to an input of a succeeding unit delay cell. At least two of the unit delay cells in the series are sequentially activated in response to an activation signal. The sequential activation may be performed by a control circuit that is connected to the series of unit delay cells.

Abstract: Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the D

Abstract: A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal. The first signal buffer has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal. The second signal buffer has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to the node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.

Abstract: An integrated circuit memory device can include a memory cell array having a plurality of memory cells, and a bit line sense amplifier configured to amplify data on a pair of bit lines from a memory cell of the memory cell array and to provide the amplified data on a data line and a complementary data line. An active load circuit includes a first load device electrically connected between the data line and a voltage source wherein an electrical resistance of the first load device is varied responsive to a voltage level of the data line. The active load circuit also includes a second load device electrically connected between the complementary data line and the voltage source wherein an electrical resistance of the second load device is varied responsive to a voltage level of the complementary data line. Related methods are also discussed.

Abstract: Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

Abstract: A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal. The first signal buffer has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal. The second signal buffer has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to the node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.

Abstract: Delay line circuits and methods include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding unit delay cell is connected to an input of a succeeding unit delay cell. At least two of the unit delay cells in the series are sequentially activated in response to an activation signal. The sequential activation may be performed by a control circuit that is connected to the series of unit delay cells.