Patents by Inventor Sungmook Lim
Sungmook Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11882703Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.Type: GrantFiled: July 15, 2021Date of Patent: January 23, 2024Assignee: SK hynix Inc.Inventors: Sungmook Lim, Dae Hwan Yun, Gil Bok Choi, Jae Hyeon Shin, In Gon Yang, Hyung Jin Choi
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Patent number: 11776657Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.Type: GrantFiled: April 23, 2021Date of Patent: October 3, 2023Assignee: SK hynix Inc.Inventors: In Gon Yang, Tae Ho Kim, Jae Hyeon Shin, Sungmook Lim
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Publication number: 20230284759Abstract: Provided is a shopping bag adopting a unique design structure, so that a user's will to re-use the shopping bag can be strengthened and the shopping bag is easy to be processed. The shopping bag entirely has an elliptical structure and comprises: a central portion on which an object is placed; a peripheral portion which surrounds the central portion and has various cut patterns formed therein; and a pair of handle portions which are symmetrically formed at both sides of the edge of the peripheral portion, wherein the specially designed cut patterns are adopted in order to relieve asymmetrical stress caused by the elliptical structure and stress concentration due to the cut patterns.Type: ApplicationFiled: January 17, 2022Publication date: September 14, 2023Inventor: Sungmook LIM
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Patent number: 11615847Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.Type: GrantFiled: February 23, 2021Date of Patent: March 28, 2023Assignee: SK hynix Inc.Inventors: Jae Hyeon Shin, In Gon Yang, Sungmook Lim
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Patent number: 11482286Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.Type: GrantFiled: March 3, 2021Date of Patent: October 25, 2022Assignee: SK hynix Inc.Inventors: Jae Hyeon Shin, Tae Ho Kim, In Gon Yang, Sungmook Lim
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Patent number: 11462272Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.Type: GrantFiled: May 7, 2021Date of Patent: October 4, 2022Assignee: SK hynix Inc.Inventors: Hyung Jin Choi, Jae Hyeon Shin, In Gon Yang, Sungmook Lim
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Patent number: 11462285Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.Type: GrantFiled: March 10, 2021Date of Patent: October 4, 2022Assignee: SK hynix Inc.Inventors: Sungmook Lim, In Gon Yang, Jae Hyeon Shin, Hyung Jin Choi
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Patent number: 11410731Abstract: Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.Type: GrantFiled: February 16, 2021Date of Patent: August 9, 2022Assignee: SK hynix Inc.Inventors: Jae Hyeon Shin, Tae Ho Kim, In Gon Yang, Sungmook Lim
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Publication number: 20220216231Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.Type: ApplicationFiled: July 15, 2021Publication date: July 7, 2022Applicant: SK hynix Inc.Inventors: Sungmook LIM, Dae Hwan YUN, Gil Bok CHOI, Jae Hyeon SHIN, In Gon YANG, Hyung Jin CHOI
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Publication number: 20220139461Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.Type: ApplicationFiled: May 7, 2021Publication date: May 5, 2022Applicant: SK hynix Inc.Inventors: Hyung Jin CHOI, Jae Hyeon SHIN, In Gon YANG, Sungmook LIM
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Publication number: 20220122687Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.Type: ApplicationFiled: April 23, 2021Publication date: April 21, 2022Applicant: SK hynix Inc.Inventors: In Gon YANG, Tae Ho KIM, Jae Hyeon SHIN, Sungmook LIM
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Publication number: 20220084612Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.Type: ApplicationFiled: March 10, 2021Publication date: March 17, 2022Applicant: SK hynix Inc.Inventors: Sungmook LIM, In Gon YANG, Jae Hyeon SHIN, Hyung Jin CHOI
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Publication number: 20220068388Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.Type: ApplicationFiled: March 3, 2021Publication date: March 3, 2022Applicant: SK hynix Inc.Inventors: Jae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
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Publication number: 20220059167Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic, The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.Type: ApplicationFiled: February 23, 2021Publication date: February 24, 2022Applicant: SK hynix Inc.Inventors: Jae Hyeon SHIN, In Gon YANG, Sungmook LIM
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Publication number: 20220051723Abstract: Provided herein is a semiconductor memory device and a method of operating the same, The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.Type: ApplicationFiled: February 16, 2021Publication date: February 17, 2022Applicant: SK hynix Inc.Inventors: Jae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
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Publication number: 20210398595Abstract: The present technology relates to a page buffer and a semiconductor memory device with the same. The page buffer includes a bit line controller connected to a bit line and configured to control a potential level of a sensing node based on a current level of the bit line during a sensing operation, and a main latch configured to latch data based on a potential of the sensing node. The bit line controller includes a first transistor connected between the bit line and a common sensing node, and a second transistor connected between a power voltage terminal and the common sensing node, and the second transistor is a PMOS transistor.Type: ApplicationFiled: November 13, 2020Publication date: December 23, 2021Applicant: SK hynix Inc.Inventors: Sungmook LIM, Hyung Jin CHOI
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Patent number: 10858746Abstract: The present inventive concept provides a method of manufacturing graphene using electrochemistry, the method including dipping a cathode including metal and an anode including graphite into an electrolyte and applying a DC power supply between the cathode and the anode, wherein the DC power supply is a DC switching power supply applying a positive (+) voltage and a negative (?) voltage alternately and repetitively. The method according to the present inventive concept can simply mass-produce high purity graphene by applying the DC switching power supply, thereby efficiently controlling the ions to peel the graphite.Type: GrantFiled: December 10, 2018Date of Patent: December 8, 2020Inventors: Wonoh Lee, Sungmook Lim, Jong Hun Han
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Publication number: 20190352787Abstract: The present inventive concept provides a method of manufacturing graphene using electrochemistry, the method including dipping a cathode including metal and an anode including graphite into an electrolyte and applying a DC power supply between the cathode and the anode, wherein the DC power supply is a DC switching power supply applying a positive (+) voltage and a negative (?) voltage alternately and repetitively. The method according to the present inventive concept can simply mass-produce high purity graphene by applying the DC switching power supply, thereby efficiently controlling the ions to peel the graphite.Type: ApplicationFiled: December 10, 2018Publication date: November 21, 2019Inventors: Wonoh LEE, Sungmook LIM, Jong Hun HAN
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Patent number: 8325002Abstract: A variety of power inductor structures are obtained by arranging a magnetic material block between a plurality of wires and a plurality of bond fingers or bond finger pairs. The power inductor structure can provide high inductance and high currents and at the same time afford smaller sizes.Type: GrantFiled: May 27, 2010Date of Patent: December 4, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Sungmook Lim, Yunjae Chong, Sungmo Kang
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Publication number: 20110291785Abstract: A variety of power inductor structures are obtained by arranging a magnetic material block between a plurality of wires and a plurality of bond fingers or bond finger pairs. The power inductor structure can provide high inductance and high currents and at the same time afford smaller sizes.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sungmook Lim, Yunjae Chong, Sungmo Kang