Patents by Inventor Sung-Nam Chang
Sung-Nam Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8436410Abstract: Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap.Type: GrantFiled: March 17, 2011Date of Patent: May 7, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Woong Kang, Sung-Nam Chang, Jin-Joo Kim, Kyong-Joo Lee, Eun-Jung Lee
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Patent number: 8362542Abstract: Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.Type: GrantFiled: July 30, 2010Date of Patent: January 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Woong Kang, Sung-Nam Chang, Jin-Joo Kim, Kyong-Joo Lee, Eun-Jung Lee
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Publication number: 20110163367Abstract: Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Inventors: Dae-Woong Kang, Sung-Nam Chang, Jin-Joo Kim, Kyong-Joo Lee, Eun-Jung Lee
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Publication number: 20100295113Abstract: Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.Type: ApplicationFiled: July 30, 2010Publication date: November 25, 2010Inventors: Dae-Woong Kang, Sung-Nam Chang, Jin-Joo Kim, Kyong-Joo Lee, Eun-Jung Lee
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Patent number: 7831427Abstract: Monitoring a spoken-word audio stream for a relevant concept is disclosed. A speech recognition engine may recognize a plurality of words from the audio stream. Function words that do not indicate content may be removed from the plurality of words. A concept may be determined from at least one word recognized from the audio stream. The concept may be determined via a morphological normalization of the plurality of words. The concept may be associated with a time related to when the at least one word was spoken. A relevance metric may be computed for the concept. Computing the relevance metric may include assessing the temporal frequency of the concept within the audio stream. The relevance metric for the concept may be based on respective confidence scores of the at least one word. The concept, time, and relevance metric may be displayed in a graphical display.Type: GrantFiled: June 20, 2007Date of Patent: November 9, 2010Assignee: Microsoft CorporationInventors: Stephen Frederick Potter, Tal Saraf, David Gareth Ollason, Steve Sung-Nam Chang
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Patent number: 7736989Abstract: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.Type: GrantFiled: July 21, 2008Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Won Chang, Sung-Nam Chang, Seung-Gun Seo, Dong-Seog Eun
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Patent number: 7700426Abstract: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.Type: GrantFiled: January 29, 2007Date of Patent: April 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Kyung Kim, Sung-Nam Chang, Dong-Seog Eun
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Patent number: 7666717Abstract: A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.Type: GrantFiled: October 5, 2006Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Sun Sel, Sung-Nam Chang, Dae-Woong Kang, Bong-Tae Park
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Patent number: 7598564Abstract: A non-volatile memory device including a barrier spacer that serves to protect a control gate, including a metal layer, from damage that may result from exposure to a cleaning solution and/or oxygen. With the barrier spacer layer, a cleaning process using a high-power cleaning solution may be used to effectively remove etch byproducts. An oxidation process may be performed to cure etch damage of an intergate dielectric pattern, a floating gate and a gate insulator. The barrier spacer and/or the oxidation process enable a non-volatile memory device having enhanced speed and reliability to be formed.Type: GrantFiled: May 31, 2006Date of Patent: October 6, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-woong Kang, Sung-nam Chang, Kwang-jae Lee
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Patent number: 7541243Abstract: Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.Type: GrantFiled: February 2, 2007Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Seog Eun, Sung-Nam Chang
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Patent number: 7508048Abstract: Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region.Type: GrantFiled: January 15, 2004Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Woong Kang, Hong-Soo Kim, Jung-Dal Choi, Kyu-Charn Park, Seong-Soon Cho, Yong-Sik Yim, Sung-Nam Chang
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Publication number: 20090029520Abstract: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.Type: ApplicationFiled: July 21, 2008Publication date: January 29, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Won CHANG, Sung-Nam Chang, Seung-Gun Seo, Dong-Seog Eun
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Publication number: 20080319750Abstract: Monitoring a spoken-word audio stream for a relevant concept is disclosed. A speech recognition engine may recognize a plurality of words from the audio stream. Function words that do not indicate content may be removed from the plurality of words. A concept may be determined from at least one word recognized from the audio stream. The concept may be determined via a morphological normalization of the plurality of words. The concept may be associated with a time related to when the at least one word was spoken. A relevance metric may be computed for the concept. Computing the relevance metric may include assessing the temporal frequency of the concept within the audio stream. The relevance metric for the concept may be based on respective confidence scores of the at least one word. The concept, time, and relevance metric may be displayed in a graphical display.Type: ApplicationFiled: June 20, 2007Publication date: December 25, 2008Applicant: Microsoft CorporationInventors: Stephen Frederick Potter, Tal Saraf, David Gareth Ollason, Steve Sung-Nam Chang
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Patent number: 7391082Abstract: A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient.Type: GrantFiled: January 25, 2006Date of Patent: June 24, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyun Shin, Kwang-Jae Lee, Sung-Nam Chang, Wang-Chul Shin
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Publication number: 20080124866Abstract: Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.Type: ApplicationFiled: February 2, 2007Publication date: May 29, 2008Inventors: Dong-Seog Eun, Sung-Nam Chang
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Publication number: 20080093650Abstract: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.Type: ApplicationFiled: January 29, 2007Publication date: April 24, 2008Inventors: Tae-Kyung Kim, Sung-Nam Chang, Dong-Seog Eun
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Patent number: 7344944Abstract: A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.Type: GrantFiled: January 27, 2006Date of Patent: March 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Charn Park, Kwang-Shik Shin, Sung-Nam Chang
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Publication number: 20070096202Abstract: Methods for forming semiconductor memory structures including air gaps between adjacent gate structures are provided. The volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures. The methods include forming an insulation layer between adjacent gate structures and subsequently etching the insulation layer to leave an air gap. Devices fabricated in accordance with the methods are also provided.Type: ApplicationFiled: October 20, 2006Publication date: May 3, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Woong KANG, Sung-Nam CHANG, Jin-Joo KIM, Kyong-Joo LEE, Eun-Jung LEE
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Publication number: 20070087496Abstract: A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.Type: ApplicationFiled: October 5, 2006Publication date: April 19, 2007Inventors: Jong-Sun Sel, Sung-Nam Chang, Dae-Woong Kang, Bong-Tae Park
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Publication number: 20070034938Abstract: A non-volatile memory device including a barrier spacer that serves to protect a control gate, including a metal layer, from damage that may result from exposure to a cleaning solution and/or oxygen. With the barrier spacer layer, a cleaning process using a high-power cleaning solution may be used to effectively remove etch byproducts. An oxidation process may be performed to cure etch damage of an intergate dielectric pattern, a floating gate and a gate insulator. The barrier spacer and/or the oxidation process enable a non-volatile memory device having enhanced speed and reliability to be formed.Type: ApplicationFiled: May 31, 2006Publication date: February 15, 2007Inventors: Dae-woong Kang, Sung-nam Chang, Kwang-jae Lee