Abstract: A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.

Abstract: A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.

Abstract: A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion.

Abstract: A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion.

Abstract: An ultra high voltage MOS transistor device includes a substrate having a first conductivity type and a first recess formed thereon, a gate positioned on the first recess, and a pair of source region and drain region having a second conductivity type formed in two sides of the gate, respectively.

Abstract: A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions.

Abstract: A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions.

Abstract: A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.

Abstract: An ultra high voltage MOS transistor device includes a substrate having a first conductivity type and a first recess formed thereon, a gate positioned on the first recess, and a pair of source region and drain region having a second conductivity type formed in two sides of the gate, respectively.

Abstract: A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.

Abstract: An ultra high voltage MOS transistor device includes a substrate having a first conductive type, a first well having a second conductive type and a second well having the first conductive type formed in the substrate, a drain region having the second conductive type formed in the first well, a source region having the second conductive type formed in the second well, a first doped region having the first conductive type formed between the second well and the substrate, an insulating layer formed in a first recess in the first well, a gate formed on the substrate between the source region and the first well, and a recessed channel region formed in the substrate underneath the gate.

Abstract: A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

Abstract: A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

Abstract: An ultra high voltage MOS transistor device includes a substrate having a first conductive type, a first well having a second conductive type and a second well having the first conductive type formed in the substrate, a drain region having the second conductive type formed in the first well, a source region having the second conductive type formed in the second well, a first doped region having the first conductive type formed between the second well and the substrate, an insulating layer formed in a first recess in the first well, a gate formed on the substrate between the source region and the first well, and a recessed channel region formed in the substrate underneath the gate.