Abstract: A field emission device (110, 210, 310, 410) includes an electron emitter (124), a first dielectric focusing layer (122) defining a first aperture (127), and a second dielectric focusing layer (123) defining a second aperture (133). Second dielectric focusing layer (123) is disposed on first dielectric focusing layer (122). The dielectric constant of second dielectric focusing layer (123) is less than the dielectric constant of first dielectric focusing layer (122). During the operation of field emission device (110, 210, 310), electron emitter (124) emits an electron beam (134), which is focused as it travels through first aperture (127) and then through second aperture (133).

Abstract: An electron emitter (121, 221, 321, 421) includes an electron emitter structure (118) having a passivation layer (120, 220, 320, 420) formed thereon. The passivation layer (120, 220, 320, 420) is made from an oxide selected from a group consisting of the oxides of Ba, Ca, Sr, In, Sc, Ti, Ir, Co, Sr, Y, Zr, Ru, Pd, Sn, Lu, Hf, Re, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Th, and combinations thereof. In the preferred embodiment, the electron emitter structure (118) is made from molybdenum, and the passivation layer (120, 220, 320, 420) is made from an emission-enhancing oxide having a work function that is less than the work function of the molybdenum.

Abstract: A method for fabricating a field emission device (200) includes the steps of forming on the surface of a substrate (110) a cathode (112), forming on the cathode (112) a dielectric layer (114), forming an emitter well (115) in the dielectric layer (114), forming within the emitter well (115) an electron emitter structure (118) having a surface (123), forming on a portion of the dielectric layer (114) a gate electrode (116), depositing on the dielectric layer (114) a sacrificial layer (210), thereafter depositing on the surface (123) of the electron emitter structure (118) a coating material (220, 320, 420) that has an emission-enhancing material, and then removing the sacrificial layer (210).

Abstract: A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produced in the layers at the mesa sidewall and the first layer overlying the mesa is in contact with the last layer overlying the substrate adjacent the mesa. A spacer of nonconductive material is formed on the discontinuity and the plurality of overlying layers are etched, using the spacer as a mask, so as to form a contact area overlying the mesa and a contact area overlying the substrate adjacent the mesa, and a semiconductor device positioned adjacent the sidewall beneath the spacer and between the contact areas.

Abstract: A field emission display (100) includes a dielectric layer (132) having a plurality of emitter wells (134), a plurality of electron emitters (136) disposed one each within the plurality of emitter wells (134), a plurality of conductive rows (138, 140, 142) disposed on the dielectric layer (132) and having sacrificial portions (154), an ion shield (139) disposed on the dielectric layer (132) and spaced apart from the sacrificial portions (154) of the plurality of conductive rows (138, 140, 142), and an anode (121) opposing the plurality of electron emitters (136) and defining a projected area (122) at the plurality of conductive rows (138, 140, 142). The sacrificial portions (154) of the plurality of conductive rows (138, 140, 142) extend beyond the projected area (122) of the anode (121).

Abstract: A method for protecting extraction electrodes (140) during processing of Spindt-tip field emitters (150, 155) includes the steps of: (i) depositing a parting layer (170) on the extraction electrodes (140) and in an interspace region (145) defined by the extraction electrodes (140), (ii) sharpening the Spindt-tip field emitters (150), (iii) depositing a layer (180) of emission-enhancing material on the sharpened field emitters (155) and on the parting layer (170), and (iv) removing the parting layer (170), thereby lifting off the emission-enhancing material from the extraction electrodes (140) and from the interspace region (145), but not from the sharpened field emitters (155).

Abstract: A field emission device (100, 200) includes an anode (190); a substrate (110); a plurality of spaced apart cathodes (120); a dielectric layer (124) disposed on the cathodes (120); a plurality of spacer pads (130, 230) disposed on the substrate (110) between adjacent cathodes (120) and including a spacer contact layer (142, 185) that defines the surfaces of the spacer pads (130, 230); a spacer (150) having a first edge (157), a second edge (155), and a conductive layer (152) disposed on the second edge (155), the first edge (157) contacting the anode (190), the conductive layer (152) contacting the spacer contact layer (142, 185) at the spacer pads (130, 230); and an electron emitter (170) disposed within the dielectric layer (124) and spaced apart from the second edge (155) of the spacer (150).

Abstract: A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

Abstract: An array of thin film piezoelectric resonators are formed on a substrate and connected in parallel to form a single piezoelectric resonator with enhanced piezoelectric coupling. The array includes a first conductive layer positioned on the substrate and defining a first electrode, a plurality of columns of piezoelectric material positioned on the conductive layer and each defining a separate piezoelectric resonator, and a second conductive layer positioned on the plurality of columns and defining a second electrode. The columns are selectively deposited or deposited as a single layer and etched into columns.

Abstract: A method of planarizing wide bandgap semiconductor devices selected from a group including SiC, GaN and diamond having a mesa defined thereon by a trench with a depth of 1 to 2 micrometers and a width of 2 to 10 micrometers. A layer of dielectric material is deposited on the substrate overlying and surrounding the mesa, to a height approximately equal to the height of the mesa and the dielectric material is etched from atop the mesa and from a surrounding area. Layers of spin on glass are deposited to fill the surrounding area and etched to achieve a planar surface including the mesa and the layer of dielectric material.

Abstract: A process of fabricating submicron features including depositing a gate metal layer on a substrate and forming a first etchable layer of material on the metal layer to define a first sidewall. A second etchable layer is deposited on the structure so as to define a second sidewall. The second etchable layer is etched so as to leave only the second sidewall and the first etchable layer is removed. The metal layer is etched using the second sidewall as an etch mask to form a submicron feature. The width of the feature depends upon the thickness of the metal layer.