Patents by Inventor Sung Sim
Sung Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240179931Abstract: A light emitting device may include a first electrode, a second electrode on the first electrode, and an emission layer between the first electrode and the second electrode, wherein the emission layer includes a first compound represented by Formula 1.Type: ApplicationFiled: July 19, 2023Publication date: May 30, 2024Inventors: CHANSEOK OH, JUNHA PARK, Kyoung SUNWOO, MinJae SUNG, MUN-KI SIM, CHANGWOONG CHU
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Publication number: 20240139003Abstract: Provided is a bioresorbable stent including a stent substrate including a bioresorbable polymer and a contrast medium containing an iodine component, coated on the stent substrate. Since the stent according to the present invention is absorbed in and removed from the human body after a predetermined time, it has excellent biodegradability since it has improved radiopacity by iodine contrast medium coating, it has a high radiography contrast and is very efficient even when a procedure is performed with real time radiography, and since it has low foreshortening and high flexibility, radial force, and re-coil, it may be useful for insertion into a blood vessel having a small diameter, an acute occlusive lesion, an imminent occlusive lesion, and the like.Type: ApplicationFiled: May 13, 2022Publication date: May 2, 2024Inventors: Myung Ho JEONG, Dae Sung PARK, Jae Un KIM, Mun Ki KIM, Doo Sun SIM, Kyung Hoon CHO, Dae Young HYUN, Jun Kyu PARK
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Publication number: 20240145772Abstract: An embodiment composition for solid electrolyte membranes of all-solid-state batteries includes a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities. An embodiment method of manufacturing a solid electrolyte membrane for an all-solid-state battery includes forming a composition including a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities and cross-linking the composition.Type: ApplicationFiled: September 14, 2023Publication date: May 2, 2024Inventors: So Yeon Kim, Yun Sung Kim, Ga Hyeon Im, Yoon Kwang Lee, Hong Seok Min, Kyu Joon Lee, Dong Won Kim, Young Jun Lee, Hui Tae Sim, Seung Bo Hong
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Patent number: 11967529Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.Type: GrantFiled: November 10, 2020Date of Patent: April 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
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Publication number: 20240130148Abstract: Provided is a light emitting device including a first electrode, a second electrode facing the first electrode, and an emission layer between the first electrode and the second electrode, wherein the emission layer includes a first compound represented by Formula 1 below.Type: ApplicationFiled: July 31, 2023Publication date: April 18, 2024Inventors: MUN-KI SIM, TAEIL KIM, JANG YEOL BAEK, MinJae SUNG, MINJUNG JUNG, Seonhyoung HUR
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Publication number: 20240114788Abstract: Embodiments provide light emitting element which includes a first electrode, a second electrode disposed on the first electrode, and an emission layer disposed between the first electrode and the second electrode, wherein the emission layer includes a polycyclic compound represented by Formula 1, which is explained in the specification:Type: ApplicationFiled: July 7, 2023Publication date: April 4, 2024Applicant: Samsung Display Co., Ltd.Inventors: MUN-KI SIM, EUNG DO KIM, TAEIL KIM, MinJae SUNG, MINJUNG JUNG, Seonhyoung HUR
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Patent number: 11945798Abstract: Provided are aminopyridine compounds and pharmaceutically acceptable compositions thereof which exhibit inhibition activity against certain mutated forms of EGFR.Type: GrantFiled: August 26, 2022Date of Patent: April 2, 2024Assignees: YUHAN CORPORATION, JANSSEN BIOTECH, INC.Inventors: Hyunjoo Lee, Su Bin Choi, Young Ae Yoon, Kwan Hoon Hyun, Jae Young Sim, Marian C. Bryan, Scott Kuduk, James Campbell Robertson, Jaekyoo Lee, Paresh Devidas Salgaonkar, Byung-Chul Suh, Jong Sung Koh, So Young Hwang
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Patent number: 11737520Abstract: Provided is a non-skid shoe capable of absorbing shock including: an outsole; a plurality of accommodation grooves formed on the outsole, the accommodation groove including a groove portion, and a penetrated portion extending from the groove portion and penetrating the outsole; a support member which is accommodated in the respective accommodation grooves, and includes a support portion disposed in the groove portion, a first guide portion formed at a center of the support portion, and a second guide portion extending from the first guide portion and penetrating a bottom surface of the support portion; a movable member which is disposed in the respective support members, and includes a latch portion and a protruding portion; a pressing member engaged to an upper portion of the first guide portion; a resilient member disposed in the first guide portion; and a midsole engaged to the top surface of the outsole.Type: GrantFiled: January 23, 2019Date of Patent: August 29, 2023Assignee: SHINWON CHEMICAL PRODUCTS CO., LTD.Inventors: Sung Sim Kim, Choon Geun Choi, Do Kyung Choi
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Patent number: 11659665Abstract: A connection structure-embedded substrate includes: a printed circuit board including a plurality of first insulating layers of which at least one has a cavity provided therein, a plurality of first wiring layers disposed as at least one of an outer portion and an inner portion of the plurality of first insulating layers, and a first build-up insulating layer disposed on an upper surface of the plurality of first insulating layers; and a connection structure at least partially disposed in the cavity. The first build-up insulating layer is disposed in the cavity, and each of a lower surface of the connection structure and a lower surface of the cavity is in contact with at least a portion of the first build-up insulating layer, respectively.Type: GrantFiled: March 30, 2021Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ho Hyung Ham, Won Seok Lee, Jae Sung Sim
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Patent number: 11557355Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: GrantFiled: February 28, 2022Date of Patent: January 17, 2023Assignee: SK hynix Inc.Inventors: Sung Hoon Cho, Jae Sung Sim, Han Soo Joo, Hee Chang Chae, Se Kyoung Choi
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Publication number: 20220408559Abstract: A printed circuit board includes: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface facing the one surface of the first insulating layer; a via penetrating through the first insulating layer to connect the first and second metal layers to each other; and a heterogeneous metal region disposed in at least one of an area in which the via is adjacent to the first insulating layer and an area in which the via is adjacent to the first metal layer, and including a material different from that of the via, wherein the heterogeneous metal region includes at least one of nickel (Ni), silicon (Si), and titanium (Ti).Type: ApplicationFiled: March 7, 2022Publication date: December 22, 2022Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hee-Joon CHUN, Jae Sung SIM, Hak Young LEE, Kwang Hee KWON, Hee Jung JUNG
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Publication number: 20220210921Abstract: A connection structure-embedded substrate includes: a printed circuit board including a plurality of first insulating layers of which at least one has a cavity provided therein, a plurality of first wiring layers disposed as at least one of an outer portion and an inner portion of the plurality of first insulating layers, and a first build-up insulating layer disposed on an upper surface of the plurality of first insulating layers; and a connection structure at least partially disposed in the cavity. The first build-up insulating layer is disposed in the cavity, and each of a lower surface of the connection structure and a lower surface of the cavity is in contact with at least a portion of the first build-up insulating layer, respectively.Type: ApplicationFiled: March 30, 2021Publication date: June 30, 2022Inventors: Ho Hyung HAM, Won Seok LEE, Jae Sung SIM
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Publication number: 20220180951Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: SK hynix Inc.Inventors: Sung Hoon CHO, Jae Sung SIM, Han Soo JOO, Hee Chang CHAE, Se Kyoung CHOI
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Patent number: 11335406Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.Type: GrantFiled: October 20, 2020Date of Patent: May 17, 2022Assignee: SK hynix Inc.Inventors: Sung Hoon Cho, Jae Sung Sim, Se Kyoung Choi
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Patent number: 11302404Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: GrantFiled: July 8, 2020Date of Patent: April 12, 2022Assignee: SK hynix Inc.Inventors: Sung Hoon Cho, Jae Sung Sim, Han Soo Joo, Hee Chang Chae, Se Kyoung Choi
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Publication number: 20210366550Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.Type: ApplicationFiled: October 20, 2020Publication date: November 25, 2021Applicant: SK hynix Inc.Inventors: Sung Hoon CHO, Jae Sung SIM, Se Kyoung CHOI
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Publication number: 20210353006Abstract: Provided is a non-skid shoe capable of absorbing shock including: an outsole; a plurality of accommodation grooves formed on the outsole, the accommodation groove including a groove portion, and a penetrated portion extending from the groove portion and penetrating the outsole; a support member which is accommodated in the respective accommodation grooves, and includes a support portion disposed in the groove portion, a first guide portion formed at a center of the support portion, and a second guide portion extending from the first guide portion and penetrating a bottom surface of the support portion; a movable member which is disposed in the respective support members, and includes a latch portion and a protruding portion; a pressing member engaged to an upper portion of the first guide portion; a resilient member disposed in the first guide portion; and a midsole engaged to the top surface of the outsole.Type: ApplicationFiled: January 23, 2019Publication date: November 18, 2021Applicant: SHINWON CHEMICAL PRODUCTS CO., LTD.Inventors: Sung Sim KIM, Choon Geun CHOI, Do Kyung CHOI
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Patent number: 11152390Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: June 16, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20210241838Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: ApplicationFiled: July 8, 2020Publication date: August 5, 2021Applicant: SK hynix Inc.Inventors: Sung Hoon CHO, Jae Sung SIM, Han Soo JOO, Hee Chang CHAE, Se Kyoung CHOI
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Patent number: 11076488Abstract: A board having an electronic component embedded therein, includes a core layer having a groove with a bottom surface, an electronic component disposed above the bottom surface of the groove and spaced apart from the bottom surface of the groove, and an insulating layer disposed on the core layer and covering at least a portion of the electronic component. The insulating layer is disposed in at least a portion of a space between the bottom surface of the groove and the electronic component.Type: GrantFiled: November 12, 2019Date of Patent: July 27, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ho Hyung Ham, Jae Sung Sim