Patents by Inventor Sung T. Ahn

Sung T. Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5342796
    Abstract: A method for preparing a semiconductor device comprises the following steps: (I) depositing at least nitride film on the whole surface of a semiconductor substrate having a field oxide film, (II) removing a portion of the nitride film from a gate-formation region to form an opening at the nitride film up to the substrate, (III) thereafter forming by selective oxidation a vertically projecting oxide film on the substrate at the opening portion, (IV) then removing all the films including the oxide film and the nitride film each covering the substrate to form a dug part of the substrate at the gate formation region, (V) providing on the dug part a gate oxide film and a gate electrode in the order, (VI) doping an impurity ion into the substrate in a manner of self-alignment using the gate electrode as a mask, and (VII) applying heat treatment to the substrate to form an impurity-diffused region.
    Type: Grant
    Filed: May 27, 1992
    Date of Patent: August 30, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Sung T. Ahn, Shigeki Hayashida
  • Patent number: 5298435
    Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: September 3, 1992
    Date of Patent: March 29, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5280185
    Abstract: A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: January 18, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5166087
    Abstract: A method of fabricating an insulating gate type field-effect transistor in which a region having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region having a high carrier density, the method comprising the steps of: forming a gate insulating film and a gate electrode on a semiconductor substrate; depositing an insulating thin film on the gate electrode and the gate insulating film to a vertical thickness; and performing from above the insulating thin film, ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness of the insulating thin film so as to form the source/drain region; wherein a horizontal thickness of the insulating thin film on opposite sides of the gate electrode is larger than a sum of a lateral diffusion distance of the source/drain region at the time of the ion implantation and a lateral diffusion distance of the source/drain region after the ion implantation.
    Type: Grant
    Filed: January 13, 1992
    Date of Patent: November 24, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seizo Kakimoto, Katsuji Iguchi, Sung T. Ahn
  • Patent number: 5095358
    Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: April 18, 1990
    Date of Patent: March 10, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5094972
    Abstract: An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.
    Type: Grant
    Filed: June 14, 1990
    Date of Patent: March 10, 1992
    Assignee: National Semiconductor Corp.
    Inventors: John M. Pierce, Sung T. Ahn