Patents by Inventor Sung Tae Lee

Sung Tae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847376
    Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Osawa, Syo Fukata, Naoto Umehara, Sung Tae Lee
  • Publication number: 20200294602
    Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 17, 2020
    Inventors: Jong-Ho LEE, Sung-Tae LEE
  • Publication number: 20200006080
    Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.
    Type: Application
    Filed: April 10, 2019
    Publication date: January 2, 2020
    Inventors: Yusuke OSAWA, Syo FUKATA, Naoto UMEHARA, Sung Tae LEE
  • Patent number: 10325713
    Abstract: An inductor includes a support having first and second coils formed on first and second surfaces thereof, respectively; a body embedding the support therein so that end portions of the first and second coils are exposed through first and second surfaces of the body opposing each other, and including a first magnetic part disposed in cores of the first and second coils and on upper and lower surfaces of the first and second coils, respectively, and second magnetic parts disposed on upper and lower surfaces of the first magnetic part, respectively; and first and second external electrodes formed on outer surfaces of the body to be electrically connected to the end portions of the first and second coils, respectively. The second magnetic part has a content of a hardening accelerator greater than that of the first magnetic part.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong Hyun Park, Sung Tae Lee
  • Patent number: 10269620
    Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 23, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Zhenyu Lu, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Sung Tae Lee, Yao-sheng Lee, Johann Alsmeier
  • Publication number: 20170309388
    Abstract: An inductor includes a support having first and second coils formed on first and second surfaces thereof, respectively; a body embedding the support therein so that end portions of the first and second coils are exposed through first and second surfaces of the body opposing each other, and including a first magnetic part disposed in cores of the first and second coils and on upper and lower surfaces of the first and second coils, respectively, and second magnetic parts disposed on upper and lower surfaces of the first magnetic part, respectively; and first and second external electrodes formed on outer surfaces of the body to be electrically connected to the end portions of the first and second coils, respectively. The second magnetic part has a content of a hardening accelerator greater than that of the first magnetic part.
    Type: Application
    Filed: February 15, 2017
    Publication date: October 26, 2017
    Inventors: Jeong Hyun PARK, Sung Tae LEE
  • Publication number: 20170236746
    Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
    Type: Application
    Filed: September 23, 2016
    Publication date: August 17, 2017
    Inventors: Jixin YU, Zhenyu LU, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Sung Tae LEE, Yao-sheng LEE, Johann ALSMEIER
  • Patent number: 9673304
    Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 6, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Michiaki Sano, Akira Nakada, Tetsuya Yamada, Manabu Hayashi, Takashi Matsubara, Sung Tae Lee, Akio Nishida
  • Patent number: 9437543
    Abstract: A contact via cavity can be filled with a lower structure and an upper structure. The lower structure can be a conductive structure that is formed by depositing a conformal conductive material, and subsequently removing an upper portion of the conformal conductive material. A disposable material portion can be formed at a bottom of the cavity to protect the bottom portion of the conformal conductive layer during removal of the upper portion. After removal of the disposable material, at least one conductive material can fill the remainder of the cavity to form the upper structure. The upper structure and the lower structure collectively constitute a contact via structure. Alternatively, the lower structure can be a dielectric spacer with an opening therethrough. The upper structure can be a conductive structure that extends through the dielectric spacer, and provides an electrically conductive vertical connection.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 6, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akira Nakada, Michiaki Sano, Motoki Kawasaki, Sung Tae Lee
  • Publication number: 20160218059
    Abstract: A contact via cavity can be filled with a lower structure and an upper structure. The lower structure can be a conductive structure that is formed by depositing a conformal conductive material, and subsequently removing an upper portion of the conformal conductive material. A disposable material portion can be formed at a bottom of the cavity to protect the bottom portion of the conformal conductive layer during removal of the upper portion. After removal of the disposable material, at least one conductive material can fill the remainder of the cavity to form the upper structure. The upper structure and the lower structure collectively constitute a contact via structure. Alternatively, the lower structure can be a dielectric spacer with an opening therethrough. The upper structure can be a conductive structure that extends through the dielectric spacer, and provides an electrically conductive vertical connection.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 28, 2016
    Inventors: Akira NAKADA, Michiaki SANO, Motoki KAWASAKI, Sung Tae LEE
  • Patent number: 8404590
    Abstract: There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: March 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Sung Tae Lee, Kazuya Dobashi
  • Publication number: 20120021538
    Abstract: There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 26, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Sung Tae Lee, Kazuya Dobashi
  • Patent number: 8094194
    Abstract: A display apparatus having a displaying part, includes a video processing part to process an input video signal into a format which can be displayed on the displaying part, and a controlling part to determine whether a video image displayed on the displaying part is a still image, and if it is determined that the video image is the still image, to control the video processing part to display the video image according to the input video signal and a predetermined after-image prevention image alternately on the displaying part. Thus, the present general inventive concept provides a display apparatus which is capable of removing an after-image effect occurring in a display panel effectively, and a control method thereof.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: January 10, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventor: Sung-tae Lee
  • Patent number: 8054383
    Abstract: A method of preventing image burn-in of a display apparatus to display an image includes detecting pixel data of a pixel of the image, calculating OSD data corresponding to the detected pixel data, generating the calculated OSD data, and merging the OSD data to the pixel data and displaying the merged OSD data in the pixel for a predetermined refresh period of time.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-tae Lee
  • Patent number: 8005517
    Abstract: A mobile communication device is provided. The mobile communication device includes a terminal body, and a speaker module located in the terminal body. The speaker module includes an enclosure located in the terminal body, the enclosure defining a chamber therein, and a speaker having a front surface and a rear surface, the speaker being located in the enclosure such that the front surface of the speaker is exposed from the enclosure and the rear surface thereof is positioned within the chamber, to allow a sound generated from the rear surface to resonate within the chamber. A mutual interference between the sound generated from the front side of the sound emission part and the sound emitted from the rear side thereof can be reduced to thereby improve the performance of the middle and low sound.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: August 23, 2011
    Assignee: LG Electronics Inc.
    Inventors: Jeong-Hoon Kang, Jin-Ho Kim, Sung-Tae Lee
  • Patent number: 7967997
    Abstract: A plasma etching method includes: plasma etching a silicon oxide film to be etched that is positioned under a multi-layer resist mask by using the multi-layer resist mask formed on a substrate to be processed; and plasma etching a glass based film positioned under the silicon oxide film by using the multi-layer resist mask. In the method a gaseous mixture of C4F6 gas and C3F8 gas as a processing gas is used in the plasma etching of the glass based layer.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: June 28, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Sung Tae Lee
  • Patent number: 7432199
    Abstract: Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate patterns, an ion implantation process that uses the gate patterns and the gate spacers as an ion mask is performed to form a plug doped region in a portion of the semiconductor substrate that is located below the wide opening. At this point, the gate spacers are formed to expose a portion of a bottom surface of the wide opening and to fill a lower portion of the narrow opening.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: October 7, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Tae Lee, Sun-Young Kim, Young-Soo Song
  • Publication number: 20080190892
    Abstract: A plasma etching method includes: plasma etching a silicon oxide film to be etched that is positioned under a multi-layer resist mask by using the multi-layer resist mask formed on a substrate to be processed; and plasma etching a glass based film positioned under the silicon oxide film by using the multi-layer resist mask. In the method a gaseous mixture of C4F6 gas and C3F8 gas as a processing gas is used in the plasma etching of the glass based layer.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 14, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Sung Tae LEE
  • Patent number: RE44942
    Abstract: A mobile communication device is provided. The mobile communication device includes a terminal body, and a speaker module located in the terminal body. The speaker module includes an enclosure located in the terminal body, the enclosure defining a chamber therein, and a speaker having a front surface and a rear surface, the speaker being located in the enclosure such that the front surface of the speaker is exposed from the enclosure and the rear surface thereof is positioned within the chamber, to allow a sound generated from the rear surface to resonate within the chamber. A mutual interference between the sound generated from the front side of the sound emission part and the sound emitted from the rear side thereof can be reduced to thereby improve the performance of the middle and low sound.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: June 10, 2014
    Assignee: LG Electronics Inc.
    Inventors: Sung-Tae Lee, Jin-Ho Kim, Jeong-Hoon Kang
  • Patent number: D887071
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: June 9, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Hye Cho Shin, Jeong Ho Son, Hyun Soo Chung, Ah Ra Cho, Chi Young Lee, Duck Su Oh, Sung Tae Lee, Ho Geol Lim