Abstract: An integrated circuit for a physically unclonable function (PUF) includes a controller configured to generate a control signal with reference to an address table, the address table representing a first mapping relationship between a first PUF cell group and a second PUF cell group having a first predetermined mismatch distance in relation to a PUF cell characteristic, and representing a second mapping relationship between a third PUF cell group and a fourth PUF cell group having a second predetermined mismatch distance in relation to the PUF cell characteristic; and a PUF block configured to provide PUF cell data groups in accordance with the first and second mapping relationships to the controller, in response to the control signal. The controller may be configured to generate an authentication key by respectively comparing the PUF cell data groups with reference data groups.

Abstract: An integrated circuit for a physically unclonable function (PUF) includes a controller configured to generate a control signal with reference to an address table, the address table representing a first mapping relationship between a first PUF cell group and a second PUF cell group having a first predetermined mismatch distance in relation to a PUF cell characteristic, and representing a second mapping relationship between a third PUF cell group and a fourth PUF cell group having a second predetermined mismatch distance in relation to the PUF cell characteristic; and a PUF block configured to provide PUF cell data groups in accordance with the first and second mapping relationships to the controller, in response to the control signal. The controller may be configured to generate an authentication key by respectively comparing the PUF cell data groups with reference data groups.

Abstract: An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.

Abstract: An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.

Abstract: A novel energy-efficient multiplication circuit using analog multipliers and adders reduces the distance data has to move and the number of times the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula to output the generate a matrix multiplication result in form of a current that is then digitized for further processing.

Abstract: An operation method of a security device which includes a plurality of physical unclonable function (PUF) cells includes selecting a target PUF cell of the plurality of PUF cells, selecting at least two reference PUF cells of the plurality of PUF cells based on a sorted list, reading a plurality of sensing data from the target PUF cell and the at least two reference PUF cells, and determining a target bit corresponding to the target PUF cell based on the plurality of sensing data to output the determined target bit.

Abstract: A security device includes a physical unclonable function (PUF) cell array including a plurality of PUF cells, and a controller configured to control the PUF cell array to generate a security key. The controller includes a receiver configured to receive raw data from the plurality of PUF cells, a mapping table generator configured to extract stable data from the received raw data by discarding unstable data of the received raw data, and generate a mapping table based on stable PUF cells corresponding to the extracted stable data, among the plurality of PUF cells, a PUF cell controller configured to read sensing data from the stable PUF cells, based on the generated mapping table, and a bit determiner configured to generate the security key, based on the read sensing data.

Abstract: A security device includes a physical unclonable function (PUF) cell array including PUF cells connected with word lines and bit lines; first decoder circuitry connecting a first bit line connected to a target PUF cell with a first data line and a second bit line connected with a reference PUF cell to a second data line; a digital-to-analog converter (DAC) control circuit outputting first and second digital codes; a first DAC between a power supply voltage and the first data line, the first DAC generating a first analog output in response to the first digital code; a second DAC between the power supply voltage and the second data line, the second DAC generating a second analog output in response to the second digital code; and a sense amplifier comparing the first analog output and the second analog output and outputting a comparison result.

Abstract: An integrated circuit for a physically unclonable function (PUF) includes a controller configured to generate a control signal with reference to an address table, the address table representing a first mapping relationship between a first PUF cell group and a second PUF cell group having a first predetermined mismatch distance in relation to a PUF cell characteristic, and representing a second mapping relationship between a third PUF cell group and a fourth PUF cell group having a second predetermined mismatch distance in relation to the PUF cell characteristic; and a PUF block configured to provide PUF cell data groups in accordance with the first and second mapping relationships to the controller, in response to the control signal. The controller may be configured to generate an authentication key by respectively comparing the PUF cell data groups with reference data groups.

Abstract: A smart card is provided. The smart card includes a peripheral circuit configured to control a fingerprint sensing array and generate a raw image, an authentication information processing module configured to process the raw image into fingerprint information for verification, a security module configured to determine whether the fingerprint information for verification matches registered fingerprint information to determine usage approval or disapproval for a payment request, and an active shield overlapping the security module. The peripheral circuit, the authentication information processing module, and the security module are integrated into one chip.

Abstract: An operation method of a security device which includes a plurality of physical unclonable function (PUF) cells includes selecting a target PUF cell of the plurality of PUF cells, selecting at least two reference PUF cells of the plurality of PUF cells based on a sorted list, reading a plurality of sensing data from the target PUF cell and the at least two reference PUF cells, and determining a target bit corresponding to the target PUF cell based on the plurality of sensing data to output the determined target bit.

Abstract: A security device includes a physical unclonable function (PUF) cell array including a plurality of PUF cells, and a controller configured to control the PUF cell array to generate a security key. The controller includes a receiver configured to receive raw data from the plurality of PUF cells, a mapping table generator configured to extract stable data from the received raw data by discarding unstable data of the received raw data, and generate a mapping table based on stable PUF cells corresponding to the extracted stable data, among the plurality of PUF cells, a PUF cell controller configured to read sensing data from the stable PUF cells, based on the generated mapping table, and a bit determiner configured to generate the security key, based on the read sensing data.

Abstract: Systems and methods allow to take advantage of the natural statistical variation of physical properties in a semiconductor device in order to create truly random, repeatable, and hard to detect cryptographic bits. This may be accomplished by recursively pairing mismatch values of Physically Unclonable Functions (PUF) elements so as to ensure that generated PUF key bits remain insensitive to environmental errors, without affecting the utilization rate of available PUF elements. The pairing process may be applied to any given hardware to generate more stable PUF bit sequences that provide a higher margin of error, increase the number of bits for a given margin of error, or any combination thereof.

Abstract: A novel energy-efficient multiplication circuit using analog multipliers and adders reduces the distance data has to move and the number of times the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula to output the generate a matrix multiplication result in form of a current that is then digitized for further processing.

Abstract: Various embodiments of the invention allow to take advantage of the natural statistical variation of physical properties in a semiconductor device in order to create truly random, repeatable, and hard to detect cryptographic bits. In certain embodiments, this is accomplished by recursively pairing mismatch values of PUF elements so as to ensure that generated PUF key bits remain insensitive to environmental errors, without affecting the utilization rate of available PUF elements. The pairing process may be applied to any given hardware to generate more stable PUF bit sequences that provide a higher margin of error, increase the number of bits for a given margin of error, or any combination thereof.

Abstract: Security devices for protecting ICs from backside security attacks. A security device includes an N? well formed in a substrate, a P+ center disposed in the central region of the N? well, and a P+ ring surrounding the N? well. To prevent latchup, a pair of inner and outer N+ rings is formed in the N? well. When a current source is applied to the P+ center, the current flows through a portion of the substrate and is picked up by the P+ ring. When an attacker mills the substrate or makes a trench in the substrate, the resistance of the substrate changes. By monitoring the voltage difference between the P+ center and P+ ring, the attempt to attack the die can be detected.

Abstract: Various embodiments of the invention allow to effectively reduce device and system power consumption in both active and inactive modes without compromising performance, without large area overhead, and at low cost. In certain embodiments, the reduction of power consumption is accomplished by combining circuit control techniques with power gating methods to reduce power loss due to leakage current.

Abstract: Various embodiments of the invention relate to secure systems and modules, and more particularly, to systems, devices and methods of generating and applying identification elements uniquely associated with memory, memory mapping and encrypted storage. These unique identification elements provide an improved, statistically random source from which keys and memory mappings may be derived. The application of these keys across various architectures result in an improvement in the security of data stored within a system.

Abstract: The invention relates to systems having linear regulators and methods of operating the systems. The system includes: a linear regulator responsive to an input voltage and operative to output a regulated voltage; a first circuit responsive to the regulated voltage and configured to operate at a first voltage difference between the regulated voltage and a ground level; and a second circuit responsive to the input voltage and the regulated voltage and configured to operate at a second voltage difference between the input voltage and the regulated voltage. The second circuit is coupled to the first circuit so that an entire portion of a current flowing through the second circuit is configured to enter into the first circuit during operation, wherein the current flowing through the second circuit bypasses the linear regulator.

Abstract: Various embodiments of the invention allow to take advantage of the natural statistical variation of physical properties in a semiconductor device in order to create truly random, repeatable, and hard to detect cryptographic bits. In certain embodiments, this is accomplished by pairing mismatch values of PUF elements so as to ensure that PUF key bits generated thereform remain insensitive to environmental errors, without affecting the utilization rate of available PUF elements.