Abstract: A method of a first user equipment (UE) may comprise: receiving a downlink (DL) reference signal transmitted by a base station using a beam included in a beam candidate group to be used for sidelink (SL) communication with a second UE; measuring a DL reference signal received power (RSRP) of the DL reference signal; determining a transmit power of a beam included in the beam candidate group based on the measured DL RSRP; and transmitting SL data to the second UE with the determined transmit power.

Abstract: An operation method of a relay node may include: receiving, from a first communication node, first data composed of n bits; receiving, from a second communication node, second data composed of m bits; in response to determining that n is greater than m, generating first T-data of m bits excluding (n-m) bits from the n-bits of the first data and first R-data of (n-m) bits; generating third data by performing a network coding operation on the first T-data and the second data; transmitting the third data to the first communication node; and transmitting the third data and the first R-data to the second communication node.

Abstract: An electroluminescent device including a first electrode and a second electrode facing each other; a light emitting layer disposed between the first electrode and the second electrode; and an electron transport layer disposed between the light emitting layer and the second electrode. The light emitting layer includes a plurality of semiconductor nanoparticles, and the electron transport layer includes a plurality of zinc oxide nanoparticles, the zinc oxide nanoparticles further include magnesium and gallium.

Abstract: The present disclosure relates to an ultraviolet light-blocking composition containing a centipede grass extract and a cosmetic composition and, more specifically, to an ultraviolet light-blocking composition comprising a centipede grass (Eremochloa ophiuroides) leaf extract as an active ingredient; and a cosmetic composition containing the ultraviolet light-blocking composition.

Abstract: A hybrid memory system may include: a volatile memory; a nonvolatile memory; and a memory controller configured to a threshold value for a read-to-write ratio according to a refresh interval of the volatile memory, and to perform migration of a page between the volatile memory and the nonvolatile memory based on the threshold value and a read-to-write ratio of the page.

Abstract: A hybrid memory system may include: a volatile memory; a nonvolatile memory; and a memory controller configured to a threshold value for a read-to-write ratio according to a refresh interval of the volatile memory, and to perform migration of a page between the volatile memory and the nonvolatile memory based on the threshold value and a read-to-write ratio of the page.

Abstract: Disclosed is a cache memory, and more particularly to a cache memory, in which a word-line voltage control logic unit and a word-line driver are added as a logic circuit between a row decoder and a word line, so that a reinforcement voltage signal having a higher level than a basic voltage signal can be applied when accessing the word line corresponding to an access time failure, thereby decreasing an access time delay in the word line in order to minimize an access failure to the cache memory due to process variation.

Abstract: Disclosed is a cache memory, and more particularly to a cache memory, in which a word-line voltage control logic unit and a word-line driver are added as a logic circuit between a row decoder and a word line, so that a reinforcement voltage signal having a higher level than a basic voltage signal can be applied when accessing the word line corresponding to an access time failure, thereby decreasing an access time delay in the word line in order to minimize an access failure to the cache memory due to process variation.

Abstract: A method, system and branch predictor for branch prediction. The system includes a processor core for executing instructions, a branch target buffer for fetching a branch address, and a branch predictor for first predicting a branch of a current instruction address and indicating to the processor core when to fetch the branch address from the branch target buffer. A branch predictor, including a branch prediction table for storing a plurality of branch prediction values of previous branch instructions, and a controller for selecting one of the plurality of branch prediction values and outputting the selected one of the plurality of branch prediction values to a processor core, the selected one of the plurality of branch prediction values indicating to the processor core when to fetch a branch address from a branch target buffer.

Abstract: In order to decode a simulation instruction in accordance with the present invention, a new decoding program is generated, which includes flat-type decoding codes for at least one of the instructions having a high occurrence frequency. The remaining instructions are decoded using tree-type decoding codes. By combining both flat-type and tree-type decoding operations in a single decoding program, simulation speed is increased while reducing memory requirements.

Abstract: A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors. The multiprocessor system may further include a control unit. If the multiprocessor system receives an access request for a data block of the memory unit from one processor. The processors may also include a processing unit. When the processor shares a data block, the processing unit may invalidate the shared data block in the cache memory, write the shared data block from the write buffer to a memory unit, and forward an interrupt completion response to a control unit.

Abstract: A microprocessor to reduce leakage power of execution units or reconfigurable cells, and method thereof are provided. The microprocessor may include a control unit for assigning an instruction, a plurality of execution units connected to the control unit, and a temperature sensor unit for acquiring temperature information of each of the plurality of execution units. The control unit may select one or more execution units according to the temperature information and assigns the instruction to one or more of the plurality of execution units.

Abstract: There are provided a controller for an instruction cache and an instruction TLB (Translation Look-aside Buffer), and a method of controlling the same.

Abstract: In order to decode a simulation instruction in accordance with the present invention, a new decoding program is generated, which includes flat-type decoding codes for at least one of the instructions having a high occurrence frequency. The remaining instructions are decoded using tree-type decoding codes. By combining both flat-type and tree-type decoding operations in a single decoding program, simulation speed is increased while reducing memory requirements.

Abstract: A microprocessor to reduce leakage power of execution units or reconfigurable cells, and method thereof are provided. The microprocessor may include a control unit for assigning an instruction, a plurality of execution units connected to the control unit, and a temperature sensor unit for acquiring temperature information of each of the plurality of execution units. The control unit may select one or more execution units according to the temperature information and assigns the instruction to one or more of the plurality of execution units.

Abstract: A method, system and branch predictor for branch prediction. The system includes a processor core for executing instructions, a branch target buffer for fetching a branch address, and a branch predictor for first predicting a branch of a current instruction address and indicating to the processor core when to fetch the branch address from the branch target buffer. A branch predictor, including a branch prediction table for storing a plurality of branch prediction values of previous branch instructions, and a controller for selecting one of the plurality of branch prediction values and outputting the selected one of the plurality of branch prediction values to a processor core, the selected one of the plurality of branch prediction values indicating to the processor core when to fetch a branch address from a branch target buffer.

Abstract: A branch prediction apparatus may include a first branch predictor for executing a first branch prediction algorithm and a second branch predictor for executing a second branch prediction algorithm. A choice predictor may generate a control signal for controlling operations of the first branch predictor and the second branch predictor. The choice predictor may also select and output a prediction result of the first branch predictor or the second branch predictor. The first branch predictor and the second branch predictor may respectively execute the prediction algorithms depending on the control signal. The choice predictor may include a shift register for shifting stored branch prediction values of the branch prediction apparatus to the left by one bit. A choice prediction table may be indexed by a value of the shift register to output a predictor selection value.

Abstract: A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors. The multiprocessor system may further include a control unit. If the multiprocessor system receives an access request for a data block of the memory unit from one processor, the control unit may forward an interrupt signal to another processor that shares the requested data block. The directory memory may store information indicating the processors that share data blocks of the memory unit. A memory controller unit may include the memory unit, the directory memory, and a control unit connected to memory unit and the directory memory. Each of the processors may include a processor core including a write buffer and a cache memory. The processors may also include a processing unit.