Patents by Inventor Sung-Yong Chung
Sung-Yong Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11975375Abstract: According to an exemplary embodiment of the present disclosure, disclosed is an aluminum coated blank that includes a first coated steel sheet; a second coated steel sheet connected to the first coated steel sheet; and a joint portion that connects the first coated steel sheet to the second coated steel plate at a boundary between the first coated steel sheet and the second coated steel sheet.Type: GrantFiled: December 3, 2020Date of Patent: May 7, 2024Assignee: Hyundai Steel CompanyInventors: Chang Yong Lee, Sung Ryul Kim, Jeong Seok Kim, Joo Sik Hyun, Yoo Dong Chung, Soon Geun Jang
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Publication number: 20240132441Abstract: The present invention relates to a leveling agent and an electrolytic composition comprising the same. When the via hole in the substrate is filled with the electrolytic composition according to the present invention, the via hole can be filled within a relatively short time while minimizing the formation of dimples or voids.Type: ApplicationFiled: July 29, 2022Publication date: April 25, 2024Inventors: Sung Wook CHUN, Bo Mook CHUNG, Dea Geun KIM, Nak Eun KO, Ju Yong SIM
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Publication number: 20240131569Abstract: According to an exemplary embodiment of the present disclosure, disclosed is an aluminum coated blank that includes a first coated steel sheet; a second coated steel sheet connected to the first coated steel sheet; and a joint portion that connects the first coated steel sheet to the second coated steel plate at a boundary between the first coated steel sheet and the second coated steel sheet.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Inventors: Chang Yong Lee, Sung Ryul Kim, Jeong Seok Kim, Joo Sik Hyun, Yoo Dong Chung
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Publication number: 20240133039Abstract: The present invention relates to a leveling agent and an electrolytic composition comprising the same. When the via hole in the substrate is filled with the electrolytic composition according to the present invention, the via hole can be filled within a relatively short time while minimizing the formation of dimples or voids.Type: ApplicationFiled: July 29, 2022Publication date: April 25, 2024Inventors: Sung Wook CHUN, Bo Mook CHUNG, Dea Geun KIM, Nak Eun KO, Ju Yong SIM
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Patent number: 11950412Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.Type: GrantFiled: February 14, 2022Date of Patent: April 2, 2024Assignee: Longitude Flash Memory Solutions LTD.Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
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Publication number: 20230180480Abstract: The present discloses includes a memory device including a first vertical plug and a second vertical plug that are arranged to be adjacent to each other, a first select line contacting the first vertical plug, a second select line over a same layer as the first select line and contacting the second vertical plug, and an isolation pattern overlapping with a portion of the first vertical plug and a portion of the second vertical plug and separating the first select line from the second select line.Type: ApplicationFiled: May 11, 2022Publication date: June 8, 2023Applicant: SK hynix Inc.Inventors: Sung Yong CHUNG, Nam Kuk KIM
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Publication number: 20230093329Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: ApplicationFiled: November 29, 2022Publication date: March 23, 2023Applicant: SK hynix Inc.Inventors: Jung Dal CHOI, Jung Shik JANG, Jin Kook KIM, Dong Sun SHEEN, Se Young OH, Ki Hong LEE, Dong Hun LEE, Sung Hoon LEE, Sung Yong CHUNG
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Publication number: 20230093683Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: ApplicationFiled: November 29, 2022Publication date: March 23, 2023Applicant: SK hynix Inc.Inventors: Jung Dal CHOI, Jung Shik JANG, Jin Kook KIM, Dong Sun SHEEN, Se Young OH, Ki Hong LEE, Dong Hun LEE, Sung Hoon LEE, Sung Yong CHUNG
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Patent number: 11545190Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: GrantFiled: November 13, 2019Date of Patent: January 3, 2023Assignee: SK hynix Inc.Inventors: Jung Dal Choi, Jung Shik Jang, Jin Kook Kim, Dong Sun Sheen, Se Young Oh, Ki Hong Lee, Dong Hun Lee, Sung Hoon Lee, Sung Yong Chung
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Publication number: 20220173116Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen LIN, Yi-Ching Jean Wu
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Patent number: 11251189Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.Type: GrantFiled: April 10, 2019Date of Patent: February 15, 2022Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
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Publication number: 20210020203Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.Type: ApplicationFiled: November 13, 2019Publication date: January 21, 2021Applicant: SK hynix Inc.Inventors: Jung Dal CHOI, Jung Shik JANG, Jin Kook KIM, Dong Sun SHEEN, Se Young OH, Ki Hong LEE, Dong Hun LEE, Sung Hoon LEE, Sung Yong CHUNG
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Patent number: 10672480Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.Type: GrantFiled: September 26, 2019Date of Patent: June 2, 2020Assignee: SK hynix Inc.Inventors: Hee Youl Lee, Kyoung Cheol Kwon, Dong Hun Lee, Min Kyu Jeong, Sung Yong Chung
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Publication number: 20200020403Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Inventors: Hee Youl LEE, Kyoung Cheol KWON, Dong Hun LEE, Min Kyu JEONG, Sung Yong CHUNG
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Patent number: 10490284Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.Type: GrantFiled: March 20, 2018Date of Patent: November 26, 2019Assignee: SK hynix Inc.Inventors: Hee Youl Lee, Kyoung Cheol Kwon, Dong Hun Lee, Min Kyu Jeong, Sung Yong Chung
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Publication number: 20190319035Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.Type: ApplicationFiled: April 10, 2019Publication date: October 17, 2019Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen LIN, Yi-Ching Jean Wu
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Patent number: 10297606Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.Type: GrantFiled: January 11, 2017Date of Patent: May 21, 2019Assignee: Cypress Semiconductor CorporationInventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
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Publication number: 20190057744Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.Type: ApplicationFiled: March 20, 2018Publication date: February 21, 2019Inventors: Hee Youl LEE, Kyoung Cheol KWON, Dong Hun LEE, Min Kyu JEONG, Sung Yong CHUNG
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Publication number: 20180032271Abstract: A semiconductor memory device includes a memory cell array including a plurality of pages, peripheral circuits programming memory cells included in a selected page of the plurality of pages into a plurality of program states, and a control logic controlling the peripheral circuits to perform a program operation, wherein the control logic controls the peripheral circuits so that a first variable pass voltage applied to a page adjacent to the selected page is different from a pass voltage applied to remaining unselected pages during a program operation for a first set program state having a low threshold voltage distribution, among the plurality of program states.Type: ApplicationFiled: January 5, 2017Publication date: February 1, 2018Inventors: Ji Hyun SEO, Eun Mee KWON, Sung Yong CHUNG
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Patent number: 9734913Abstract: A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.Type: GrantFiled: March 7, 2016Date of Patent: August 15, 2017Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Jong Ho Lee, Ho Jung Kang, Nag Yong Choi, Byeong Il Han, Kyoung Jin Park, Sung Yong Chung