Abstract: A data verification system including a circuit verifies that unlocking data generated by a microprocessor to be written into the ASIC before a memory write is valid. The microprocessor is programmed to generate an ASIC address when unlocking data is to be written to the ASIC and to encrypt and decrypt that data. The verifying circuit unit receives the encrypted data and decrypts the encrypted data and compares the decrypted data with the encrypted data. The verifying circuit generating an enable signal only if the comparison is true. An address decoding unit is provided for receiving the memory address signal and causing a memory write enable signal to be generated for the memory unit only if the verifying circuit unit has generated an enable signal. Registers unit in communication with the data bus and the verifying circuit unit are provided for writing decryption parameters in the register unit in accordance with the programming of the microprocessor during power-up of the microprocessor.