Abstract: Disclosed is an integrated circuit that includes clock generation circuitry which generates a master clock signal and at least one other clock signal. The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit component receives the master clock signal at a first component block to create a first time domain for the first component block and receives the other clock signal at a second component block to create a second time domain for the second component block. Bypass logic creates a bypass path to allow the second component block to receive the master clock signal such that the clock domain of the second component block is the same as the clock domain of the first component block such that signals can be transferred between the clock domains with reduced latency.

Abstract: According to one embodiment of the invention, a method is provided in which memory requests from a first component and a second component are received. The memory requests are issued by the first component and the second component to access one or more memory devices via a memory controller. The memory requests received from the first component are accumulated in a first queue and the memory requests received from the second component are accumulated in a second queue, respectively. The memory requests accumulated in the first queue are sent to the memory controller for processing as a block of memory requests. The memory requests accumulated in the second queue are sent to the memory controller for processing as a block of memory requests.

Abstract: Disclosed is an integrated circuit that includes clock generation circuitry which generates a master clock signal and at least one other clock signal. The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit component receives the master clock signal at a first component block to create a first time domain for the first component block and receives the other clock signal at a second component block to create a second time domain for the second component block. Bypass logic creates a bypass path to allow the second component block to receive the master clock signal such that the clock domain of the second component block is the same as the clock domain of the first component block such that signals can be transferred between the clock domains with reduced latency.

Abstract: Disclosed is an integrated circuit that includes clock generation circuitry which generates a master clock signal and at least one other clock signal. The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit component receives the master clock signal at a first component block to create a first time domain for the first component block and receives the other clock signal at a second component block to create a second time domain for the second component block. Bypass logic creates a bypass path to allow the second component block to receive the master clock signal such that the clock domain of the second component block is the same as the clock domain of the first component block such that signals can be transferred between the clock domains with reduced latency.

Abstract: According to one embodiment of the invention, a method is provided in which memory requests from a first component and a second component are received. The memory requests are issued by the first component and the second component to access one or more memory devices via a memory controller. The memory requests received from the first component are accumulated in a first queue and the memory requests received from the second component are accumulated in a second queue, respectively. The memory requests accumulated in the first queue are sent to the memory controller for processing as a block of memory requests. The memory requests accumulated in the second queue are sent to the memory controller for processing as a block of memory requests.

Abstract: Disclosed is an integrated circuit that includes clock generation circuitry which generates a master clock signal and at least one other clock signal. The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit component receives the master clock signal at a first component block to create a first time domain for the first component block and receives the other clock signal at a second component block to create a second time domain for the second component block. Bypass logic creates a bypass path to allow the second component block to receive the master clock signal such that the clock domain of the second component block is the same as the clock domain of the first component block such that signals can be transferred between the clock domains with reduced latency.