Abstract: A differential receiver includes a feedback circuit connected between an output node and one common node of the differential receiver to reduce the bandwidth and reject noise for a specific interval of time. In operation, a differential receiver bias current is controlled responsive to an output signal at the output node. Bias current is turned on during a steady-state mode with respect to the output signal, and is turned off, for a given delay period, in response to a transition mode with respect to the output signal.

Abstract: A voltage translator circuit for low level to high level voltage translation includes a plurality of transistors coupled to an inverter for receiving a common input signal at an input node of the plurality of transistors and passing a translated output signal to the output node of the plurality of transistors. A latch circuit is connected between a first node at the output node of the plurality of transistors and a second node that is connected to a feedback element at an input side of the plurality of transistors to form a feedback circuit that minimizes static power dissipation.