Abstract: A method of and an apparatus for determining the correctness of the calibration of an automatic test arrangement and correcting errors in the automatic test arrangement. The electrical length is determined from the tester driver of the automatic test arrangement to the socket pin of the tester interface unit, from the tester driver to a grounding point of the device under test, from the tester driver to the tester interface unit, and with the tester interface unit output pin connected to ground by a shorting block from the tester driver through the shorting block ground. The difference between the first electrical length and the second electrical length is compared with the difference between the first electrical length and the third electrical length, and the result is evaluated to determine the correctness of the calibration of the automatic test arrangement.

Abstract: A method of and an apparatus for designing a test environment and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated. An adjustment might be made to the virtual calibration of the virtual test environment and/or to the virtual device, or both, and the design of the actual device might be improved. The invention can be implemented on a properly programmed general purpose processing system or on a special purpose system.

Abstract: Tester derating factor (TDF) arrangements and methodologies providing improvements in semiconductor start-to-finish manufacturing arrangements, especially within DV testing and in the world of designing of devices and virtual simulation.

Abstract: A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing case of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.