Patents by Inventor Sunil K. Singh

Sunil K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180204929
    Abstract: Structures for a field-effect transistor and methods for forming a field-effect transistor. An interlayer dielectric layer is formed on a substrate. An energy removal film is formed on the interlayer dielectric layer, and at least one metal gate layer is formed on the energy removal film. After the at least one metal gate layer is polished, the energy removal film is removed from the interlayer dielectric layer. The removal of the energy removal film may remove metal residues generated by the polishing of the at least one metal gate layer so that the top surface of the interlayer dielectric layer is not contaminated by the metal residues.
    Type: Application
    Filed: January 17, 2017
    Publication date: July 19, 2018
    Inventors: Shiv K. Mishra, Sunil K. Singh
  • Publication number: 20180158723
    Abstract: Methods of lithographic patterning a dielectric layer. A first resist layer is formed on a hardmask layer, and a second resist layer is formed on the first resist layer. The second resist layer is patterned to form a first opening, which is transferred from the second resist layer to the first resist layer. The second resist layer is removed from the first resist layer after the first opening is transferred from the second resist layer to the first resist layer. The first resist layer is patterned to form a second opening laterally displaced in the first resist layer from the first opening. The first resist layer is comprised of a metal oxide photoresist that is removable selective to the hardmask layer. The hardmask layer and the dielectric layer may be subsequently patterned using first resist layer.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 7, 2018
    Inventors: Ravi Srivastava, Sunil K. Singh
  • Publication number: 20180025936
    Abstract: Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.
    Type: Application
    Filed: July 20, 2016
    Publication date: January 25, 2018
    Inventors: Sunil K. Singh, Sohan S. Mehta, Sherjang Singh, Ravi P. Srivastava
  • Publication number: 20170025347
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Application
    Filed: February 12, 2016
    Publication date: January 26, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 9293363
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Publication number: 20150332959
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Application
    Filed: July 21, 2015
    Publication date: November 19, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 9117822
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 25, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 6325808
    Abstract: A robotic system for minimally invasive surgery includes a surgical tool and a docking station for restraining movement of the surgical tool to four degrees of freedom about an incision point in a patient. The docking station includes a plurality of actuators for moving the surgical tool relative to the incision in the patient, and a controller operably connected to the actuators so that movement of the surgical tool may be collaboratively controllable both actively by the controller and manually by a surgeon. Desirably, the surgical tool and the docking station are releasably attachable together. Also disclosed is a computer implemented method employing a first docking station attachable to a suturing surgical tool and a second docking station attachable to gripping surgical tool for autonomously tying a knot in suturing.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: December 4, 2001
    Assignee: Advanced Realtime Control Systems, Inc.
    Inventors: Christopher J. Bernard, Hyosig Kang, Barton L. Sachs, Sunil K. Singh, John T. Wen