Patents by Inventor Sunil Kumar Singh
Sunil Kumar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9576894Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.Type: GrantFiled: June 3, 2015Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang
-
Publication number: 20170047290Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.Type: ApplicationFiled: August 12, 2015Publication date: February 16, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar SINGH, Ravi Prakash SRIVASTAVA, Nicholas Robert STOKES
-
Publication number: 20170047248Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.Type: ApplicationFiled: November 1, 2016Publication date: February 16, 2017Inventors: Jonathan Lee RULLAN, Sunil Kumar SINGH
-
Publication number: 20170025270Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar SINGH, Shesh Mani PANDEY
-
Patent number: 9524935Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.Type: GrantFiled: May 13, 2015Date of Patent: December 20, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jonathan Lee Rullan, Sunil Kumar Singh
-
Publication number: 20160358851Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang
-
Publication number: 20160336264Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Jonathan Lee RULLAN, Sunil Kumar SINGH
-
Publication number: 20160272642Abstract: The present invention provides a process for the preparation of linagliptin, a compound of Formula I, the process comprising deprotecting a compound of Formula II wherein R1 and R2 together with the nitrogen to which they are attached form a phthalimido group, wherein the aromatic ring of the phthalimido group is substituted with one or more R3 substituents selected from the group consisting of halogen, alkyl, nitro and amino; or R1 is H and R2 is selected from the group consisting of trialkylsilyl, 2-trialkylsilylethoxycarbamates, acetyl, trihaloacetyl, 9-fluorenylmethoxycarbonyl, trityl, alkylsulfonyl, arylsulfonyl, diphenylphosphine and sulfonylethoxycarbonyl.Type: ApplicationFiled: March 22, 2016Publication date: September 22, 2016Inventors: Sunil Kumar Singh, Sachin Srivastava, Shekhar Bhaskar Bhirud
-
Publication number: 20160211174Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.Type: ApplicationFiled: March 29, 2016Publication date: July 21, 2016Inventors: Sunil Kumar Singh, Chung-Ju Lee, Tien-I Bao
-
Publication number: 20160190003Abstract: A method of reducing defects in and improving reliability of Back-End-Of-Line (BEOL) metal fill includes providing a starting metallization structure for semiconductor device(s), the metallization structure including a bottom layer of contact(s) surrounded by a dielectric material. The starting metallization structure further includes an etch-stop layer over the bottom layer, a layer of dielectric material over the etch-stop layer, a first layer of hard mask material over the dielectric layer, a layer of work function hard mask material over the first hard mask layer, a second layer of hard mask material over the work function hard mask layer, via(s) to the first hard mask layer and other via(s) into the etch-stop layer. The method further includes protecting the other via(s) while removing the second hard mask layer and the layer of work function hard mask material, and filling the vias with metal.Type: ApplicationFiled: April 1, 2015Publication date: June 30, 2016Applicant: GLOBALFOUNDRIES INC.Inventor: Sunil Kumar SINGH
-
Patent number: 9362162Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).Type: GrantFiled: August 14, 2014Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Teck Jung Tang, Mark Alexander Zaleski
-
Patent number: 9353114Abstract: Provided is a process for the preparation of linagliptin of Formula I, comprising deprotecting a compound of Formula II wherein R1 and R2 together with the nitrogen to which they are attached form a phthalimido group, wherein the aromatic ring of the phthalimido group is substituted with one or more R3 substituents selected from the group consisting of halogen, alkyi, nitro and amino; or R1 is H and R2 is selected from the group consisting of trialkylsilyl, 2-trialkylsilylethoxycarbamates, acetyl, trihaloacetyl, 9-fluorenylmethoxycarbonyl, trityl, alkylsulfonyl, arylsulfonyl, diphenylphosphine and sulfonylethoxycarbonyl.Type: GrantFiled: August 6, 2013Date of Patent: May 31, 2016Assignee: Glenmark Pharmaceuticals LimitedInventors: Sunil Kumar Singh, Sachin Srivastava, Shekhar Bhaskar Bhirud
-
Patent number: 9318377Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.Type: GrantFiled: January 3, 2014Date of Patent: April 19, 2016Assignee: Taiwan Semiconductor Manufacutring Co., Ltd.Inventors: Sunil Kumar Singh, Chung-Ju Lee, Tien-I Bao
-
Publication number: 20160049327Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar SINGH, Ravi Prakash SRIVASTAVA, Teck Jung TANG, Mark Alexander ZALESKI
-
Publication number: 20150348907Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Inventors: Sunil Kumar SINGH, Matthew HERRICK, Teck Jung TANG, Dewei XU
-
Patent number: 9142451Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.Type: GrantFiled: September 16, 2013Date of Patent: September 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Sunil Kumar Singh, Matthew Herrick, Teck Jung Tang, Dewei Xu
-
Publication number: 20150239887Abstract: Provided is a process for the preparation of linagliptin of Formula I, comprising deprotecting a compound of Formula II wherein R1 and R2 together with the nitrogen to which they are attached form a phthalimido group, wherein the aromatic ring of the phthalimido group is substituted with one or more R3 substituents selected from the group consisting of halogen, alkyi, nitro and amino; or R1 is H and R2 is selected from the group consisting of trialkylsilyl, 2-trialkylsilylethoxycarbamates, acetyl, trihaloacetyl, 9-fluorenylmethoxycarbonyl, trityl, alkylsulfonyl, arylsulfonyl, diphenylphosphine and sulfonylethoxycarbonyl.Type: ApplicationFiled: August 6, 2013Publication date: August 27, 2015Applicant: Glenmark Generics LimitedInventors: Sunil Kumar Singh, Sachin Srivastava, Shekhar Bhaskar Bhirud
-
Patent number: 9093501Abstract: A method of forming a semiconductor device includes forming a plurality of substantially equal-spaced first spacers having a first pitch over a substrate and forming first metal interconnecting wires utilizing the first spacers. The method also includes forming a plurality of substantially equal-spaced second spacers in such a way to abut, respectively, the plurality of first metal interconnecting wires and define a plurality of substantially equal-spaced trenches. A plurality of second metal interconnecting wires are disposed, respectively, within the trenches and the second spacers are removed, thereby defining a plurality of substantially equal-spaced channels.Type: GrantFiled: July 2, 2014Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sunil Kumar Singh, Hsin-Chieh Yao, Chung-Ju Lee, Hsiang-Huan Lee
-
Patent number: 9002215Abstract: A coherent optical receiver measures a portion of a spectra of a multi-channel optical signal that includes at least one signal adjacent to a selected signal. The coherent optical receiver determines structure and bandwidth information for the measured portion of spectra, and determines one or more filter parameters for the selected signal based on the structure and bandwidth information of the at least one signal adjacent to the selected signal. The coherent optical receiver adjusts one or more active filter parameters of a carrier phase estimator in the optical coherent receiver to have values corresponding to the determined one or more filter parameters.Type: GrantFiled: July 11, 2013Date of Patent: April 7, 2015Assignee: Oclaro, Inc.Inventor: Sunil Kumar Singh Khatana
-
Publication number: 20150076705Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.Type: ApplicationFiled: September 16, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Sunil Kumar SINGH, Matthew HERRICK, Teck Jung TANG, Dewei XU