Abstract: Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for M physical streaming buffer locations, where N is greater than M. When a fetch within the processor misses the instruction cache, the fetch address is placed in the streaming buffer. When the data has been fetched from the external memory, it is returned to the streaming buffer and placed into one of the M physical buffer locations. The data within the streaming buffer is returned to the instruction cache of the processor only if it is to be used in accordance with the computer program being executed.

Abstract: An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit.

Abstract: A partially blocking data cache having improved microprocessor performance while maintaining data consistency between external memory and cache memory. The data cache of the present invention is used in a computer system and is partially blocking in that this cache will block the execution of any store instructions subsequent to an outstanding load instruction that missed the cache. The present invention offers increased microprocessor efficiency by allowing execution of subsequent load instructions while less than a predetermined number of preceding load instructions are still outstanding. The present invention utilizes a counter within the data cache unit to track the number of outstanding load misses. The present invention provides increased performance without undue or overly complex modifications to existing caching systems.