Patents by Inventor Sunil Saxena

Sunil Saxena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240104424
    Abstract: The present disclosure involves systems, software, and computer implemented methods for an artificial intelligence work center for ERP data. One example method includes receiving scenario and model settings for an artificial intelligence model for a predictive scenario. A copy of the dataset is processed based on settings to generate a prepared dataset that is provided with the settings to a predictive analytical library. A trained model trained and evaluation data for the trained model is received from the predictive analytical library. A request is received to generate a prediction for the predictive scenario for a target field for a record of the dataset. The record of the dataset is provided to the trained model and a prediction for the target field for the record the dataset is received from the model. The prediction is included for presentation in a user interface that displays information from the dataset.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Mohit V. Gadkari, Ankur Malik, Sunil S. Parvatikar, Simona Marincei, Dalibor Knis, Anirudh Prasad, Kopal Jauhari, Saurabh Saxena, Yatish Nagaraja, Pankaj Kumar Agrawal, Long Qian, Varun Verma
  • Publication number: 20240068112
    Abstract: The present invention relates to reusable metal substrate for photoelectrochemical solar water splitting applications. The process comprises preparing a surface of the metal substrate, coating the surface of the metal substrate using photoactive semiconductor thin films, forming a working electrode, scaling-up of the working electrode, and re-using the metal substrate. The present invention has advantages such as higher current, better handling, capability to reuse and capability of direct geometrical scale-up of the electrodes.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Applicant: INDIAN OIL CORPORATION LIMITED
    Inventors: Sunil SACHDEV, Gopichand TALASILA, Vinay TIWARI, Umish SRIVASTVA, Deepak SAXENA
  • Patent number: 7061237
    Abstract: An apparatus and method for remote NMR/MRI spectroscopy having an encoding coil with a sample chamber, a supply of signal carriers, preferably hyperpolarized xenon and a detector allowing the spatial and temporal separation of signal preparation and signal detection steps. This separation allows the physical conditions and methods of the encoding and detection steps to be optimized independently. The encoding of the carrier molecules may take place in a high or a low magnetic field and conventional NMR pulse sequences can be split between encoding and detection steps. In one embodiment, the detector is a high magnetic field NMR apparatus. In another embodiment, the detector is a superconducting quantum interference device. A further embodiment uses optical detection of Rb—Xe spin exchange. Another embodiment uses an optical magnetometer using non-linear Faraday rotation. Concentration of the signal carriers in the detector can greatly improve the signal to noise ratio.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: June 13, 2006
    Assignee: The Regents of the University of California
    Inventors: Alexander Pines, Sunil Saxena, Adam Moule, Megan Spence, Juliette A. Seeley, Kimberly L. Pierce, Song-I Han, Josef Granwehr
  • Publication number: 20030077224
    Abstract: An apparatus and method for remote NMR/MRI spectroscopy having an encoding coil with a sample chamber, a supply of signal carriers, preferably hyperpolarized xenon and a detector allowing the spatial and temporal separation of signal preparation and signal detection steps. This separation allows the physical conditions and methods of the encoding and detection steps to be optimized independently. The encoding of the carrier molecules may take place in a high or a low magnetic field and conventional NMR pulse sequences can be split between encoding and detection steps. In one embodiment, the detector is a high magnetic field NMR apparatus. In another embodiment, the detector is a superconducting quantum interference device. A further embodiment uses optical detection of Rb-Xe spin exchange. Another embodiment uses an optical magnetometer using non-linear Faraday rotation. Concentration of the signal carriers in the detector can greatly improve the signal to noise ratio.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 24, 2003
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Alexander Pines, Sunil Saxena, Adam Moule, Megan Spence, Juliette A. Seeley, Kimberly L. Pierce, Song-I Han, Josef Granwehr
  • Patent number: 6430670
    Abstract: The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: August 6, 2002
    Assignee: Hewlett-Packard Co.
    Inventors: William R. Bryg, Stephen G. Burger, James O. Hays, John M. Kessenich, Jonathan K. Ross, Gary N. Hammond, Sunil Saxena, Koichi Yamada
  • Patent number: 6393544
    Abstract: A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address.
    Type: Grant
    Filed: October 31, 1999
    Date of Patent: May 21, 2002
    Assignee: Institute for the Development of Emerging Architectures, L.L.C.
    Inventors: William R. Bryg, Stephen G. Burger, Gary N. Hammond, James O. Hays, Jerome C. Huck, Jonathan K. Ross, Sunil Saxena, Koichi Yamada
  • Patent number: 6216214
    Abstract: The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: April 10, 2001
    Assignee: Institute for the Development of Emerging Architectures, L.L.C.
    Inventors: William R. Bryg, Stephen G. Burger, James O. Hays, John M. Kessenich, Jonathan K. Ross, Gary N. Hammond, Sunil Saxena, Koichi Yamada
  • Patent number: 6065114
    Abstract: A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: May 16, 2000
    Assignee: Idea Corporation
    Inventors: Achmed Rumi Zahir, Jonathan K. Ross, Carol Thompson, Cary Coutant, Prasad Raje, Sunil Saxena
  • Patent number: 5699543
    Abstract: A method and an apparatus for profile guided TLB's (translation look-aside buffer) and cache optimization in an operating system. A typical operating system has a working set of information for any application which is running at some time. This working set of information can be written out by the operating system in some section of the object file. Once this information is in the object file, it may be utilized by the operating system in various ways. The method and apparatus decreases TLB misses for the benchmarks, disables infrequently used pages from disturbing the caches, and provides better rates on caches. This and many other advantages of the invention allow an increased efficiency and optimization of a given operating system.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: December 16, 1997
    Assignee: Intel Corporation
    Inventor: Sunil Saxena