Abstract: Embodiments provide a fast multi-agent reinforcement learning (RL) pipeline that runs the full RL workflow end-to-end on a single GPU, using a single store of data for simulation roll-outs, inference, and training. Specifically, simulations and agents in each simulation are run in tandem, taking advantage of the parallel capabilities of the GPU. This way, the costly GPU-CPU communication and copying is significantly reduced, and simulation sampling and learning rates are in turn improved. In this way, a large number of simulations may be concurrently run on the GPU, thus largely improving efficiency of the RL training.

Abstract: Solar array fault detection, classification, and localization using deep neural nets is provided. A fault-identifying neural network uses a cyber-physical system (CPS) approach to fault detection in photovoltaic (PV) arrays. Customized neural network algorithms are deployed in feedforward neural networks for fault detection and identification from monitoring devices that sense data and actuate each individual module in a PV array. This approach improves efficiency by detecting and classifying a wide variety of faults and commonly occurring conditions (e.g., eight faults/conditions concurrently) that affect power output in utility scale PV arrays.

Abstract: Dropout and pruned neural networks for fault classification in photovoltaic (PV) arrays are provided. Automatic detection of solar array faults leads to reduced maintenance costs and increased efficiencies. Embodiments described herein address the problem of fault detection, localization, and classification in utility-scale PV arrays. More specifically, neural networks are developed for fault classification, which have been trained using dropout regularizers. These neural networks are examined and assessed, then compared with other classification algorithms. In order to classify a wide variety of faults, a set of unique features are extracted from PV array measurements and used as inputs to a neural network. Example approaches to neural network pruning are described, illustrating trade-offs between model accuracy and complexity. This approach promises to improve the accuracy of fault classification and elevate the efficiency of PV arrays.

Abstract: Solar array fault detection, classification, and localization using deep neural nets is provided. Embodiments use a cyber-physical system (CPS) approach to fault detection in photovoltaic (PV) arrays. Customized neural network algorithms are deployed in feedforward neural networks for fault detection and identification from monitoring devices that sense data and actuate at each individual module in a PV array. This approach improves efficiency by detecting and classifying a wide variety of faults and commonly occurring conditions (e.g., eight faults/conditions concurrently) that affect power output in utility scale PV arrays.

Abstract: An approach for spending allocation, executed by one or more processors to provide one or more monetary output values in response to a request for determining spending allocation in a digital marketing channel, is provided. The approach fits one or more models to train a business environment simulator. The approach generates a supervised learning policy. The approach evolves a supervised learning policy into a distribution estimator policy by adjusting network weights of the supervised learning policy. The approach generates an optimized policy by evolving the distribution estimator policy through interaction with the business environment simulator. The approach determines a profit uplift of the optimized policy by comparing the optimized policy and the supervised learning policy. Further, in response to the optimized policy outperforming the supervised learning policy, the approach deploys the optimized policy in a live environment.

Abstract: A current carrying system for use in transporting electrical current between a plurality of electrical devices is provided. The current carrying system includes a busbar having a first axial end, a second axial end, an electrically conductive shaft extending from the first axial end to the second axial end, and at least one cooling feature defined in at least a portion of the electrically conductive shaft. The current carrying system also includes a casing that defines a busbar channel configured to receive the busbar such that the casing at least partially circumscribes the busbar. The current carrying system also includes an air vent defined by the at least one cooling feature and the casing, wherein the air vent is in flow communication with ambient air, and the cooling feature is configured to facilitate a flow of air from the ambient air through the air vent.

Abstract: An approach for spending allocation, executed by one or more processors to provide one or more monetary output values in response to a request for determining spending allocation in a digital marketing channel, is provided. The approach fits one or more models to train a business environment simulator. The approach generates a supervised learning policy. The approach evolves a supervised learning policy into a distribution estimator policy by adjusting network weights of the supervised learning policy. The approach generates an optimized policy by evolving the distribution estimator policy through interaction with the business environment simulator. The approach determines a profit uplift of the optimized policy by comparing the optimized policy and the supervised learning policy. Further, in response to the optimized policy outperforming the supervised learning policy, the approach deploys the optimized policy in a live environment.

Abstract: A current carrying system for use in transporting electrical current between a plurality of electrical devices is provided. The current carrying system includes a busbar having a first axial end, a second axial end, an electrically conductive shaft extending from the first axial end to the second axial end, and at least one cooling feature defined in at least a portion of the electrically conductive shaft. The current carrying system also includes a casing that defines a busbar channel configured to receive the busbar such that the casing at least partially circumscribes the busbar. The current carrying system also includes an air vent defined by the at least one cooling feature and the casing, wherein the air vent is in flow communication with ambient air, and the cooling feature is configured to facilitate a flow of air from the ambient air through the air vent.

Abstract: A system (for controlling cooling of an alternator) comprises a control system, an alternator, and a blower fan, the alternator having a stator and a rotor. The control system is adapted to estimate one or more temperatures of the stator and/or rotor of the alternator using a thermal model. The control system is also adapted to control the blower fan to cool the alternator by providing a specified amount of air flow across the stator and rotor of the alternator, based on the estimated one or more temperatures of the stator and/or rotor.

Abstract: A current carrying system for use in transporting electrical current between a plurality of electrical devices is provided. The current carrying system includes a busbar having a first axial end, a second axial end, an electrically conductive shaft extending from the first axial end to the second axial end, and at least one cooling feature defined in at least a portion of the electrically conductive shaft. The current carrying system also includes a casing that defines a busbar channel configured to receive the busbar such that the casing at least partially circumscribes the busbar. The current carrying system also includes an air vent defined by the at least one cooling feature and the casing, wherein the air vent is in flow communication with ambient air, and the cooling feature is configured to facilitate a flow of air from the ambient air through the air vent.

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts termination impedance automatically to obtain a tuned termination. The termination adaptation is realized with a ‘biased’ bang-bang phase detector (BBPD) that biases the weights applied to UP and DOWN outputs of the phase detector. Through an optimization process, the system locks to data eye corners, and thereby is able to optimize termination though a predetermined criteria, such as signal to noise ratio (SNR), horizontal eye (H-) margin, vertical eye (V-) margin or joint SNR and H-/V-margin optimization. As part of the receiver equalization, adaptive termination tuning is performed after the SerDes receiver (RX) path is initially powered-up by tuning the termination above and below its current initial setting and performing the optimization process.

Abstract: An apparatus for recovering a clock from a data signal includes an out-of-lock detector configured to detect when a receiver data clock has a frequency offset with respect to a transmitter data clock associated with the data signal, an out-of-lock counter configured to count out-of-lock conditions for the receiver data clock, and a loop filter configured to correct the frequency offset in the receiver data clock based at least in part on the count of out-of-lock conditions.

Abstract: Described embodiments provide for, in a receiver circuit, an adaptation process that adjusts the IQ-skew automatically to obtain proper eye centering in a data eye, thereby maximizing horizontal margin of the eye. The IQ-skew adaptation algorithm is realized with a ‘biased’ bang-bang phase detector (BBPD) oof a clock and data recovery circuit (CDR) that biases the weights applied to UP and DOWN outputs of the phase detector, rather than treating them equally. By weighting the BBPD UPs and DOWNs differently, the system locks to the left and right inner corners, and thereby is able to locate the center of the inner eye.

Abstract: A current carrying system for use in transporting electrical current between a plurality of electrical devices is provided. The current carrying system includes a busbar having a first axial end, a second axial end, an electrically conductive shaft extending from the first axial end to the second axial end, and at least one cooling feature defined in at least a portion of the electrically conductive shaft. The current carrying system also includes a casing that defines a busbar channel configured to receive the busbar such that the casing at least partially circumscribes the busbar. The current carrying system also includes an air vent defined by the at least one cooling feature and the casing, wherein the air vent is in flow communication with ambient air, and the cooling feature is configured to facilitate a flow of air from the ambient air through the air vent.

Abstract: A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract: A system (for controlling cooling of an alternator) comprises a control system, an alternator, and a blower fan, the alternator having a stator and a rotor. The control system is adapted to estimate one or more temperatures of the stator and/or rotor of the alternator using a thermal model. The control system is also adapted to control the blower fan to cool the alternator by providing a specified amount of air flow across the stator and rotor of the alternator, based on the estimated one or more temperatures of the stator and/or rotor.

Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.

Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.