Patents by Inventor Sunil Wickramanayaka

Sunil Wickramanayaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508619
    Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 22, 2022
    Assignee: Agency for Science, Technology and Research
    Inventors: Hongyu Li, Ling Xie, Ser Choong Chong, Sunil Wickramanayaka
  • Publication number: 20200411379
    Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.
    Type: Application
    Filed: January 24, 2019
    Publication date: December 31, 2020
    Inventors: Hongyu Li, Ling Xie, Ser Choong Chong, Sunil Wickramanayaka
  • Patent number: 10249593
    Abstract: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 2, 2019
    Assignee: Agency for Science, Technology and Research
    Inventors: Sunil Wickramanayaka, Ling Xie, Jerry Jie Li Aw
  • Publication number: 20190031502
    Abstract: There is provided a method of bonding a first substrate and a second substrate, the method comprising: providing an aluminium (Al) connection having a first width on one side of a first substrate; providing a germanium (Ge) connection having a second width on one side of a second substrate, wherein the second width is larger than the first width; and bonding the Al connection on the first substrate and the Ge connection on the second substrate by eutectic bonding of at least a portion of the Al connection and at least a portion of the Ge connection to form an Al—Ge eutectic melt, wherein the Al—Ge eutectic melt is confined within the second width of the Ge connection.
    Type: Application
    Filed: January 26, 2017
    Publication date: January 31, 2019
    Inventors: Vivek CHIDAMBARAM, Li Yan SIOW, Qing Xin ZHANG, Sunil WICKRAMANAYAKA
  • Patent number: 10134607
    Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 20, 2018
    Assignee: Agency for Science, Technology and Research
    Inventors: Vivek Chidambaram, Sunil Wickramanayaka, Jinghui Xu, Zhipeng Ding, Li Yan Siow
  • Publication number: 20170309584
    Abstract: A method for bonding a first substrate and a second substrate, the first substrate having at least one first connection extending from one side of the first substrate, the method comprising fabricating a first adhesive material around and along a height of the at least one first connection; and bonding the at least one first connection, the first adhesive material, and the second substrate.
    Type: Application
    Filed: October 23, 2015
    Publication date: October 26, 2017
    Applicants: Agency for Science, Technology and Research, Agency for Science, Technology and Research
    Inventors: Ling Xie, Sunil Wickramanayaka
  • Publication number: 20170178929
    Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.
    Type: Application
    Filed: July 9, 2015
    Publication date: June 22, 2017
    Inventors: Vivek CHIDAMBARAM, Sunil WICKRAMANAYAKA, Jinghui XU, Zhipeng DING, Li Yan SIOW
  • Patent number: 9613928
    Abstract: An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: April 4, 2017
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventor: Sunil Wickramanayaka
  • Publication number: 20170084570
    Abstract: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.
    Type: Application
    Filed: June 22, 2015
    Publication date: March 23, 2017
    Inventors: Sunil Wickramanayaka, Ling Xie, Jerry Jie Li Aw
  • Publication number: 20160155720
    Abstract: An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.
    Type: Application
    Filed: July 16, 2014
    Publication date: June 2, 2016
    Inventor: Sunil Wickramanayaka
  • Patent number: 8986522
    Abstract: A wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter of a wafer loaded on the wafer stage, the wafer stage outer-ring has an inner diameter at the upper side of the outer-ring which is larger than the diameter of the wafer loaded on the wafer stage, and the upper surface of the outer-ring lies above the upper surface of the wafer loaded on the wafer stage.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: March 24, 2015
    Assignee: Canon Anelva Corporation
    Inventor: Sunil Wickramanayaka
  • Publication number: 20110253048
    Abstract: A wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter of a wafer loaded on the wafer stage, the wafer stage outer-ring has an inner diameter at the upper side of the outer-ring which is larger than the diameter of the wafer loaded on the wafer stage, and the upper surface of the outer-ring lies above the upper surface of the wafer loaded on the wafer stage.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 20, 2011
    Applicant: Canon Anelva Corporation
    Inventor: Sunil WICKRAMANAYAKA
  • Patent number: 7848077
    Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: December 7, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
  • Patent number: 7816283
    Abstract: A method of depositing a high permittivity dielectric film on a doped silicon or silicon compound layer of a wafer. The method includes a first step of nitriding a specific element (A) such as hafnium Hf to form a nitride film (AxNy) on the silicon layer, wherein the specific element (A) and nitrogen (N) in the nitride film (AxNy) have a predetermined fraction relationship between x and y; a second step of oxidizing the nitride film in a oxygen atmosphere to form the dielectric film (AON).
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 19, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Sunil Wickramanayaka, Naoki Yamada
  • Patent number: 7791857
    Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: September 7, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
  • Patent number: 7724493
    Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: May 25, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
  • Publication number: 20100046134
    Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.
    Type: Application
    Filed: October 28, 2009
    Publication date: February 25, 2010
    Applicant: CANON ANELVA CORPORATION
    Inventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
  • Patent number: 7625472
    Abstract: A plasma-assisted sputter deposition system includes a reactor 1 into which a process gas is introduced; a doughnut-shaped electrode to be sputtered by plasma, in which a lower surface thereof is angled to a surface of a wafer; a spinning plate that spin on its central axis while moving over a circle above the doughnut-shaped electrode, in which the spinning plate contains magnet arrangement; an electrical power sources connected to the doughnut-shaped electrode, and a wafer holder for placing a wafer for film deposition, which is at rest during the film deposition.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: December 1, 2009
    Assignee: Canon Anelva Corporation
    Inventor: Sunil Wickramanayaka
  • Patent number: 7623334
    Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: November 24, 2009
    Assignee: Canon Anelva Corporation
    Inventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
  • Publication number: 20090218217
    Abstract: A method of depositing a high permittivity dielectric film on a doped silicon or silicon compound layer of a wafer. The method includes a first step of nitriding a specific element (A) such as hafnium Hf to form a nitride film (AxNy) on the silicon layer, wherein the specific element (A) and nitrogen (N) in the nitride film (AxNy) have a predetermined fraction relationship between x and y; a second step of oxidizing the nitride film in a oxygen atmosphere to form the dielectric film (AON).
    Type: Application
    Filed: April 7, 2009
    Publication date: September 3, 2009
    Applicant: CANON ANELVA CORPORATION
    Inventors: Sunil Wickramanayaka, Naoki Yamada