Patents by Inventor Sunil Wickramanayaka
Sunil Wickramanayaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11508619Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.Type: GrantFiled: January 24, 2019Date of Patent: November 22, 2022Assignee: Agency for Science, Technology and ResearchInventors: Hongyu Li, Ling Xie, Ser Choong Chong, Sunil Wickramanayaka
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Publication number: 20200411379Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.Type: ApplicationFiled: January 24, 2019Publication date: December 31, 2020Inventors: Hongyu Li, Ling Xie, Ser Choong Chong, Sunil Wickramanayaka
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Patent number: 10249593Abstract: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.Type: GrantFiled: June 22, 2015Date of Patent: April 2, 2019Assignee: Agency for Science, Technology and ResearchInventors: Sunil Wickramanayaka, Ling Xie, Jerry Jie Li Aw
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Publication number: 20190031502Abstract: There is provided a method of bonding a first substrate and a second substrate, the method comprising: providing an aluminium (Al) connection having a first width on one side of a first substrate; providing a germanium (Ge) connection having a second width on one side of a second substrate, wherein the second width is larger than the first width; and bonding the Al connection on the first substrate and the Ge connection on the second substrate by eutectic bonding of at least a portion of the Al connection and at least a portion of the Ge connection to form an Al—Ge eutectic melt, wherein the Al—Ge eutectic melt is confined within the second width of the Ge connection.Type: ApplicationFiled: January 26, 2017Publication date: January 31, 2019Inventors: Vivek CHIDAMBARAM, Li Yan SIOW, Qing Xin ZHANG, Sunil WICKRAMANAYAKA
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Patent number: 10134607Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.Type: GrantFiled: July 9, 2015Date of Patent: November 20, 2018Assignee: Agency for Science, Technology and ResearchInventors: Vivek Chidambaram, Sunil Wickramanayaka, Jinghui Xu, Zhipeng Ding, Li Yan Siow
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Publication number: 20170309584Abstract: A method for bonding a first substrate and a second substrate, the first substrate having at least one first connection extending from one side of the first substrate, the method comprising fabricating a first adhesive material around and along a height of the at least one first connection; and bonding the at least one first connection, the first adhesive material, and the second substrate.Type: ApplicationFiled: October 23, 2015Publication date: October 26, 2017Applicants: Agency for Science, Technology and Research, Agency for Science, Technology and ResearchInventors: Ling Xie, Sunil Wickramanayaka
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Publication number: 20170178929Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.Type: ApplicationFiled: July 9, 2015Publication date: June 22, 2017Inventors: Vivek CHIDAMBARAM, Sunil WICKRAMANAYAKA, Jinghui XU, Zhipeng DING, Li Yan SIOW
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Patent number: 9613928Abstract: An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.Type: GrantFiled: July 16, 2014Date of Patent: April 4, 2017Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventor: Sunil Wickramanayaka
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Publication number: 20170084570Abstract: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.Type: ApplicationFiled: June 22, 2015Publication date: March 23, 2017Inventors: Sunil Wickramanayaka, Ling Xie, Jerry Jie Li Aw
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Publication number: 20160155720Abstract: An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.Type: ApplicationFiled: July 16, 2014Publication date: June 2, 2016Inventor: Sunil Wickramanayaka
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Patent number: 8986522Abstract: A wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter of a wafer loaded on the wafer stage, the wafer stage outer-ring has an inner diameter at the upper side of the outer-ring which is larger than the diameter of the wafer loaded on the wafer stage, and the upper surface of the outer-ring lies above the upper surface of the wafer loaded on the wafer stage.Type: GrantFiled: June 27, 2011Date of Patent: March 24, 2015Assignee: Canon Anelva CorporationInventor: Sunil Wickramanayaka
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Publication number: 20110253048Abstract: A wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter of a wafer loaded on the wafer stage, the wafer stage outer-ring has an inner diameter at the upper side of the outer-ring which is larger than the diameter of the wafer loaded on the wafer stage, and the upper surface of the outer-ring lies above the upper surface of the wafer loaded on the wafer stage.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Applicant: Canon Anelva CorporationInventor: Sunil WICKRAMANAYAKA
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Patent number: 7848077Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: GrantFiled: October 28, 2009Date of Patent: December 7, 2010Assignee: Canon Anelva CorporationInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Patent number: 7816283Abstract: A method of depositing a high permittivity dielectric film on a doped silicon or silicon compound layer of a wafer. The method includes a first step of nitriding a specific element (A) such as hafnium Hf to form a nitride film (AxNy) on the silicon layer, wherein the specific element (A) and nitrogen (N) in the nitride film (AxNy) have a predetermined fraction relationship between x and y; a second step of oxidizing the nitride film in a oxygen atmosphere to form the dielectric film (AON).Type: GrantFiled: June 1, 2005Date of Patent: October 19, 2010Assignee: Canon Anelva CorporationInventors: Sunil Wickramanayaka, Naoki Yamada
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Patent number: 7791857Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: GrantFiled: December 30, 2008Date of Patent: September 7, 2010Assignee: Canon Anelva CorporationInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Patent number: 7724493Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: GrantFiled: October 22, 2008Date of Patent: May 25, 2010Assignee: Canon Anelva CorporationInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Publication number: 20100046134Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: ApplicationFiled: October 28, 2009Publication date: February 25, 2010Applicant: CANON ANELVA CORPORATIONInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Patent number: 7625472Abstract: A plasma-assisted sputter deposition system includes a reactor 1 into which a process gas is introduced; a doughnut-shaped electrode to be sputtered by plasma, in which a lower surface thereof is angled to a surface of a wafer; a spinning plate that spin on its central axis while moving over a circle above the doughnut-shaped electrode, in which the spinning plate contains magnet arrangement; an electrical power sources connected to the doughnut-shaped electrode, and a wafer holder for placing a wafer for film deposition, which is at rest during the film deposition.Type: GrantFiled: January 11, 2005Date of Patent: December 1, 2009Assignee: Canon Anelva CorporationInventor: Sunil Wickramanayaka
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Patent number: 7623334Abstract: An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.Type: GrantFiled: June 17, 2003Date of Patent: November 24, 2009Assignee: Canon Anelva CorporationInventors: Shigeru Mizuno, Masahito Ishihara, Sunil Wickramanayaka, Naoki Miyazaki
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Publication number: 20090218217Abstract: A method of depositing a high permittivity dielectric film on a doped silicon or silicon compound layer of a wafer. The method includes a first step of nitriding a specific element (A) such as hafnium Hf to form a nitride film (AxNy) on the silicon layer, wherein the specific element (A) and nitrogen (N) in the nitride film (AxNy) have a predetermined fraction relationship between x and y; a second step of oxidizing the nitride film in a oxygen atmosphere to form the dielectric film (AON).Type: ApplicationFiled: April 7, 2009Publication date: September 3, 2009Applicant: CANON ANELVA CORPORATIONInventors: Sunil Wickramanayaka, Naoki Yamada