Patents by Inventor Sunitha Venkataraman

Sunitha Venkataraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fast triggering electrostatic discharge protection
    Patent number: 11804708
    Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 31, 2023
    Assignee: NVIDIA CORP.
    Inventors: Jauwen Chen, Sunitha Venkataraman, Ting Ku
  • FAST TRIGGERING ELECTROSTATIC DISCHARGE PROTECTION
    Publication number: 20210281067
    Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Applicant: NVIDIA Corp.
    Inventors: Jauwen Chen, Sunitha Venkataraman, Ting Ku
  • Compensated well ESD diodes with reduced capacitance
    Patent number: 10497695
    Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 3, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, Jr.
  • COMPENSATED WELL ESD DIODES WITH REDUCED CAPACITANCE
    Publication number: 20170133361
    Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 11, 2017
    Inventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, JR.
  • Compensated well ESD diodes with reduced capacitance
    Patent number: 9589959
    Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, Jr.
  • Transistor assisted ESD diode
    Patent number: 9281304
    Abstract: An integrated circuit includes a diode/bipolar ESD protection device. The diode/bipolar ESD device includes at least one gate separated ESD diode and at least one gate spaced ESD bipolar transistor coupled in parallel between a fixed voltage and an input/output pin.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: March 8, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, Jr.
  • Compensated well ESD diodes with reduced capacitance
    Patent number: 8941181
    Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, Jr.
  • COMPENSATED WELL ESD DIODES WITH REDUCED CAPACITANCE
    Publication number: 20150008523
    Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, JR.