Patents by Inventor Sunity K. Sharma
Sunity K. Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230201945Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.Type: ApplicationFiled: March 7, 2023Publication date: June 29, 2023Inventors: Michael Riley VINSON, Calvin CHEN, Divyakant P. KADIWALA, Sunity K. SHARMA
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Patent number: 11597042Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.Type: GrantFiled: November 20, 2018Date of Patent: March 7, 2023Assignee: Averatek CorporationInventors: Michael Riley Vinson, Calvin Chen, Divyakant P Kadiwala, Sunity K Sharma
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Patent number: 11549184Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.Type: GrantFiled: October 1, 2021Date of Patent: January 10, 2023Assignee: Averatek CorporationInventors: Sunity K. Sharma, Shinichi Iketani
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Publication number: 20220418113Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.Type: ApplicationFiled: August 26, 2022Publication date: December 29, 2022Inventors: Michael Riley Vinson, Sunity K. Sharma, Haris Basit, Shinichi Iketani
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Publication number: 20220025520Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.Type: ApplicationFiled: October 1, 2021Publication date: January 27, 2022Inventors: Sunity K. SHARMA, Shinichi IKETANI
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Patent number: 11142825Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.Type: GrantFiled: February 3, 2020Date of Patent: October 12, 2021Assignee: AVERATEK CORPORATIONInventors: Sunity K. Sharma, Shinichi Iketani
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Publication number: 20210259112Abstract: Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 ?m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 ?m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Inventors: Shinichi IKETANI, Sunity K. SHARMA, Gary Lawrence BORGES, Michael Riley VINSON
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Publication number: 20210045252Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.Type: ApplicationFiled: April 10, 2020Publication date: February 11, 2021Inventors: Haris BASIT, Michael Riley VINSON, Sunity K. SHARMA, Shinichi IKETANI, Divyakant KADIWALA
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Publication number: 20200248311Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.Type: ApplicationFiled: February 3, 2020Publication date: August 6, 2020Inventors: Sunity K. SHARMA, Shinichi IKETANI
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Publication number: 20200232098Abstract: Methods of patterning electroless metals on a substrate are presented. The substrate is covered by a blocking reagent. After formation of a catalyst blocking layer on the substrate, portions of the catalyst blocking layer are removed to form a circuit pattern. A catalyst is placed the surfaces of both the catalyst blocking layer and the exposed substrate. The catalyst blocking layer prevents or reduces catalytic activity of the catalyst. Electroless metal plating is performed to plate a metal at the active portions of the catalyst.Type: ApplicationFiled: January 21, 2020Publication date: July 23, 2020Inventors: Michael Riley VINSON, Sunity K. SHARMA, Shinichi IKETANI, Calvin CHEN, Shalaka RAHANGDALE
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Publication number: 20200190670Abstract: Devices, systems, and methods are contemplated for depositing metals to the surface of a substrate. A first precursor ink including a metal is applied to a surface of the substrate, and the precursor ink is reduced to deposit the metal to the substrate, preferably by thermal reduction, forming a first metal layer. A second precursor ink having a second metal is then applied to the substrate, at least partially over the first metal layer. The second precursor ink is then reduced, typically by chemical reduction, depositing the second metal over the first metal layer in a globular fashion. Precursor inks are also disclosed having an alkyl metal carboxylate, a cyclic amine, and at least one of an ester, a hydrocarbon, or an ether.Type: ApplicationFiled: December 13, 2019Publication date: June 18, 2020Inventors: Sunity K SHARMA, Calvin CHEN, Shinichi IKETANI, Michael Riley VINSON
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Publication number: 20190152002Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.Type: ApplicationFiled: November 20, 2018Publication date: May 23, 2019Inventors: Michael Riley VINSON, Calvin CHEN, Divyakant P KADIWALA, Sunity K. SHARMA
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Publication number: 20180332713Abstract: Devices produced by patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate is covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: ApplicationFiled: July 23, 2018Publication date: November 15, 2018Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Patent number: 10034386Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: GrantFiled: June 23, 2017Date of Patent: July 24, 2018Assignee: AVERATEK CORPORATIONInventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Publication number: 20170354040Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: ApplicationFiled: June 23, 2017Publication date: December 7, 2017Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Patent number: 9699914Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: GrantFiled: October 20, 2015Date of Patent: July 4, 2017Assignee: AVERATEK CORPORATIONInventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Publication number: 20170159184Abstract: Devices and methods for metalizing temperature sensitive materials including fabrics are provided. Contemplated method begins with a step of applying a catalyst solution on the temperature-sensitive material to form an at least partially catalyst-coated substrate. Then the catalyst-coated substrate is incubated at a relatively low temperature. Optionally, in some embodiments, the low temperature incubated substrate is incubated at a relatively high temperature. Then, a layer of an electroless metal is deposited on the at least partially catalyst-coated substrate using an electroless metal deposition technique.Type: ApplicationFiled: December 7, 2016Publication date: June 8, 2017Inventors: Sunity K. SHARMA, Michael Riley VINSON, Divyakant P. KADIWALA
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Publication number: 20160113121Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.Type: ApplicationFiled: October 20, 2015Publication date: April 21, 2016Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
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Publication number: 20140083748Abstract: A system and method for forming conductive lines on a substrate comprising depositing a precursor onto at least a portion of the substrate, depositing a thin layer of conductive material over the precursor, forming a negative-patterned mask over a portion of the thin layer of conductive material to form an exposed pattern, forming conductive lines in the exposed pattern, removing the patterned mask thereby uncovering an exposed portion of the conductive layer that substantially corresponds to the negative pattern portion, and removing the exposed portion of the conductive layer so as to uncover substrate that substantially corresponds to the exposed portion.Type: ApplicationFiled: December 3, 2013Publication date: March 27, 2014Applicant: SRI InternationalInventors: Sunity K. SHARMA, Francesco FORNASIERO, Jaspreet Singh DHAU
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Patent number: 8628818Abstract: A system and method for forming conductive lines on a substrate comprising depositing a precursor onto at least a portion of the substrate, depositing a thin layer of conductive material over the precursor, forming a negative-patterned mask over a portion of the thin layer of conductive material to form an exposed pattern, forming conductive lines in the exposed pattern, removing the patterned mask thereby uncovering an exposed portion of the conductive layer that substantially corresponds to the negative pattern portion, and removing the exposed portion of the conductive layer so as to uncover substrate that substantially corresponds to the exposed portion.Type: GrantFiled: June 19, 2008Date of Patent: January 14, 2014Assignee: SRI InternationalInventors: Sunity K. Sharma, Francesco Fornasiero, Jaspreet Singh Dhau