Patents by Inventor Sunity K. Sharma

Sunity K. Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230201945
    Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 29, 2023
    Inventors: Michael Riley VINSON, Calvin CHEN, Divyakant P. KADIWALA, Sunity K. SHARMA
  • Patent number: 11597042
    Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 7, 2023
    Assignee: Averatek Corporation
    Inventors: Michael Riley Vinson, Calvin Chen, Divyakant P Kadiwala, Sunity K Sharma
  • Patent number: 11549184
    Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 10, 2023
    Assignee: Averatek Corporation
    Inventors: Sunity K. Sharma, Shinichi Iketani
  • Publication number: 20220418113
    Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 29, 2022
    Inventors: Michael Riley Vinson, Sunity K. Sharma, Haris Basit, Shinichi Iketani
  • Publication number: 20220025520
    Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 27, 2022
    Inventors: Sunity K. SHARMA, Shinichi IKETANI
  • Patent number: 11142825
    Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: October 12, 2021
    Assignee: AVERATEK CORPORATION
    Inventors: Sunity K. Sharma, Shinichi Iketani
  • Publication number: 20210259112
    Abstract: Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 ?m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 ?m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.
    Type: Application
    Filed: February 12, 2021
    Publication date: August 19, 2021
    Inventors: Shinichi IKETANI, Sunity K. SHARMA, Gary Lawrence BORGES, Michael Riley VINSON
  • Publication number: 20210045252
    Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.
    Type: Application
    Filed: April 10, 2020
    Publication date: February 11, 2021
    Inventors: Haris BASIT, Michael Riley VINSON, Sunity K. SHARMA, Shinichi IKETANI, Divyakant KADIWALA
  • Publication number: 20200248311
    Abstract: Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 6, 2020
    Inventors: Sunity K. SHARMA, Shinichi IKETANI
  • Publication number: 20200232098
    Abstract: Methods of patterning electroless metals on a substrate are presented. The substrate is covered by a blocking reagent. After formation of a catalyst blocking layer on the substrate, portions of the catalyst blocking layer are removed to form a circuit pattern. A catalyst is placed the surfaces of both the catalyst blocking layer and the exposed substrate. The catalyst blocking layer prevents or reduces catalytic activity of the catalyst. Electroless metal plating is performed to plate a metal at the active portions of the catalyst.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 23, 2020
    Inventors: Michael Riley VINSON, Sunity K. SHARMA, Shinichi IKETANI, Calvin CHEN, Shalaka RAHANGDALE
  • Publication number: 20200190670
    Abstract: Devices, systems, and methods are contemplated for depositing metals to the surface of a substrate. A first precursor ink including a metal is applied to a surface of the substrate, and the precursor ink is reduced to deposit the metal to the substrate, preferably by thermal reduction, forming a first metal layer. A second precursor ink having a second metal is then applied to the substrate, at least partially over the first metal layer. The second precursor ink is then reduced, typically by chemical reduction, depositing the second metal over the first metal layer in a globular fashion. Precursor inks are also disclosed having an alkyl metal carboxylate, a cyclic amine, and at least one of an ester, a hydrocarbon, or an ether.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 18, 2020
    Inventors: Sunity K SHARMA, Calvin CHEN, Shinichi IKETANI, Michael Riley VINSON
  • Publication number: 20190152002
    Abstract: Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 23, 2019
    Inventors: Michael Riley VINSON, Calvin CHEN, Divyakant P KADIWALA, Sunity K. SHARMA
  • Publication number: 20180332713
    Abstract: Devices produced by patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate is covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
  • Patent number: 10034386
    Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 24, 2018
    Assignee: AVERATEK CORPORATION
    Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
  • Publication number: 20170354040
    Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 7, 2017
    Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
  • Patent number: 9699914
    Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 4, 2017
    Assignee: AVERATEK CORPORATION
    Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
  • Publication number: 20170159184
    Abstract: Devices and methods for metalizing temperature sensitive materials including fabrics are provided. Contemplated method begins with a step of applying a catalyst solution on the temperature-sensitive material to form an at least partially catalyst-coated substrate. Then the catalyst-coated substrate is incubated at a relatively low temperature. Optionally, in some embodiments, the low temperature incubated substrate is incubated at a relatively high temperature. Then, a layer of an electroless metal is deposited on the at least partially catalyst-coated substrate using an electroless metal deposition technique.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 8, 2017
    Inventors: Sunity K. SHARMA, Michael Riley VINSON, Divyakant P. KADIWALA
  • Publication number: 20160113121
    Abstract: Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 21, 2016
    Inventors: Mihir Reddy, Michael Riley Vinson, Sunity K. Sharma
  • Publication number: 20140083748
    Abstract: A system and method for forming conductive lines on a substrate comprising depositing a precursor onto at least a portion of the substrate, depositing a thin layer of conductive material over the precursor, forming a negative-patterned mask over a portion of the thin layer of conductive material to form an exposed pattern, forming conductive lines in the exposed pattern, removing the patterned mask thereby uncovering an exposed portion of the conductive layer that substantially corresponds to the negative pattern portion, and removing the exposed portion of the conductive layer so as to uncover substrate that substantially corresponds to the exposed portion.
    Type: Application
    Filed: December 3, 2013
    Publication date: March 27, 2014
    Applicant: SRI International
    Inventors: Sunity K. SHARMA, Francesco FORNASIERO, Jaspreet Singh DHAU
  • Patent number: 8628818
    Abstract: A system and method for forming conductive lines on a substrate comprising depositing a precursor onto at least a portion of the substrate, depositing a thin layer of conductive material over the precursor, forming a negative-patterned mask over a portion of the thin layer of conductive material to form an exposed pattern, forming conductive lines in the exposed pattern, removing the patterned mask thereby uncovering an exposed portion of the conductive layer that substantially corresponds to the negative pattern portion, and removing the exposed portion of the conductive layer so as to uncover substrate that substantially corresponds to the exposed portion.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: January 14, 2014
    Assignee: SRI International
    Inventors: Sunity K. Sharma, Francesco Fornasiero, Jaspreet Singh Dhau