Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.

Abstract: In one embodiment, a processor comprises a prefetcher comprising a plurality of trackers, a tracker of the plurality of trackers to store a prefetch mask to indicate which cache lines of a sector of a sectored cache have been prefetched from a system memory to the sectored cache; and a prefetch issuer comprising circuitry, the prefetch issuer to generate a prefetch request to prefetch cache lines of the sector of the sectored cache from the system memory into the sectored cache based on a prefetch confidence metric associated with the sector of the sectored cache.

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.

Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.

Abstract: An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Abstract: Disclosed is a multi-core processor that includes a processor core, a graphics core, and a cache controller. The cache controller receives a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in a cache. The cache controller sends, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device. The cache controller receives a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache. The cache controller locks the way in the second set in response to the second request.

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Abstract: Disclosed is a multi-core processor that includes a processor core, a graphics core, and a cache controller. The cache controller receives a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in a cache. The cache controller sends, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device. The cache controller receives a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache. The cache controller locks the way in the second set in response to the second request.

Abstract: A method performed by a processor is described. The method may include identifying a graphics processing unit (GPU) phase of a frame, using said identified GPU phase to obtain frequency scalability information for said identified GPU phase, and determining whether to change a frequency at which a GPU is to draw said frame within said phase based on said frequency scalability information.

Abstract: Disclosed is a cache locking system that includes a cache controller that is operable to receive a first request from a device to lock a first way in the cache. The cache controller is operable to determine that the first way in the cache is not lockable by the device. The cache controller is also operable to send, to the device, a rejection of the first request. The cache controller is further operable to receive a second request from the device to lock a second way in the cache. The cache controller is operable to lock the second way in the cache in response to the second request.

Abstract: Disclosed is a cache locking system that includes a cache controller that is operable to receive a first request from a device to lock a first way in the cache. The cache controller is operable to determine that the first way in the cache is not lockable by the device. The cache controller is also operable to send, to the device, a rejection of the first request. The cache controller is further operable to receive a second request from the device to lock a second way in the cache. The cache controller is operable to lock the second way in the cache in response to the second request.

Abstract: Methods and apparatus relating to adaptive admission control for on die interconnect are described. In one embodiment, admission control logic determines whether to cause a change in an admission rate of requests from one or more sources of data based at least in part on comparison of a threshold value and resource utilization information. The resource utilization information is received from a plurality of resources that are shared amongst the one or more sources of data. The threshold value is determined based at least in part on a number of the plurality of resources that are determined to be in a congested condition. Other embodiments are also disclosed.

Abstract: A method performed by a processor is described. The method includes drawing a frame by performing the following: a) identifying a GPU phase; b) using said identified GPU phase to obtain frequency scalability information for said identified GPU phase; c) determining whether changing a frequency at which said GPU draws said frame within said phase is appropriate based on said frequency scalability information.